Fujitsu MB90460 Series, Hardware Manual, Page: 455 / 739

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CHAPTER 16 PWC Timer
16.3 PWC Timer Pins
This section describes the pins of the PWC timer and provides a pin block diagram.
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PWC Timer Pins
The pins of the PWC timer are shared with the general-purpose ports. Table 16.3-1 lists the functions of
the pins, I/O format, and settings required to use the 16-bit reload timer.
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Block Diagram of the PWC Timer Pins
Figure 16.3-1 shows the block diagram of the PWC timer 0 pins.
Figure 16.3-1 Block Diagram of the PWC Timer 0 Pins
Table 16.3-1 16-bit PWC Timer Pins
Pin name Pin function I/O format Pull-up option Standby control Settings required for pins
P06/PWI0
Port 0 input-output /
timer input
CMOS output /
CMOS input
Selection
allowed
Available
Setting for the input port
(DDR0: bit6 = 0)
P07/PWO0
Port 0 input-output /
timer output
Setting for timer enable
(PWCSL0: MOD2 to MOD0 not
equal 0)
P22/PWI1
Port 2 input-output /
timer input
CMOS output /
CMOS
hysteresis input
Not
provided
Setting for the input port
(DDR2: bit2 = 0)
P23/PWO1
Port 2 input-output /
timer output
Setting for timer enable
(PWCSL1: MOD2 to MOD0 not
equal 0)
Inter
n
a
l d
a
t
a
bus
Port d a t a regi s ter (PDR)
PDR re a d
PDR write
O u tp u t l a tch
DDR re a d
DDR write
Direction l a tch
Port d a t a direction regi s ter (DDR)
Pin
S t a nd b y control ( S PL = 1)
Re s o u rce o u tp u t
Re s o u rce o u tp u t en ab le
RDR
P u ll- u p re s i s tor
A b o u t 50k
Direct re s o u rce inp u t