Fujitsu MB90460 Series, Hardware Manual, Page: 440 / 739

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CHAPTER 15 MULTI-PULSE GENERATOR
15.6.5 Operation of DTTI1 Input Control
This section describes the operation of the DTTI1 Input Control Circuit.
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Operation of DTTI1 Input Control
The DTTI1 circuit controls the output of the value of PDRx (PORTx Data Register) to the pin OPTx which
is multiplexed with the PORTx where OPTx is enable by setting OPEx = 1. The operation mode is enabled
by the DTIE bit (bit15) of the Output Control Register (OPCR).
Note:
Before the DTTI1 circuit is in effect, make sure that the PORTx which is multiplexed with the OPTx
is configured as an output port by setting its Data Direction Register.
When the DTIE bit (bit14) of the Output Control Register (OPCR) is set to "1", the waveform output at
OPT5 to OPT0 pins are enabled by the valid level of the DTTI1 pin. When the low input level is placed at
the DTTI1 pin, the output of OPTx is fixed at the inactive level. The software can set the inactive level for
each OPTX pin in PDRx of PORTx, the OPTx pin is then drived by the data written in the PDRx of
PORTx.
Even while the output is fixed at the inactive level by the input of the DTTI1 pin, the timer keeps running,
the position detection function does not stop and the data transfer from the Output Data Buffer Register
(OPDBR) to the Output Data Register (OPDR) is continued for waveform generation, but no waveform is
outputted to the OPT5 to OPT0 pins.
Figure 15.6-25 shows the DTTI1 circuit block diagram and Figure 15.6-26 shows the DTTI1 circuit timing
diagram when D1,D0 is set to "00
B
".
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DTTI1 Circuit Block Diagram
Figure 15.6-25 DTTI1 Circuit Block Diagram
N-CYCLE DELAY
CIRCUIT
DTISP
NOISE CANCELLATION
SELECTOR
DTTI1 INTERRURT AND
CONTROL GENERATOR
INPUT ENANLE OR
DTIE
DISABLE SELECTOR
DTTI1 PIN
NRSL
D1
D0
N can be 4, 8, 16, 32
depending on the
setting of D1,D0 bits
in the Noise Cacellation
Register (NCCR).
DTIF