Fujitsu MB90460 Series, Hardware Manual, Page: 291 / 739

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CHAPTER 13 16-BIT PPG TIMER
■
16-bit PPG Timer Interrupts and EI
2
OS
Table 13.5-2 lists the 16-bit PPG timer interrupts and EI
2
OS.
■
EI
2
OS Function of the 16-bit PPG Timer
Since the 16-bit PPG timer has a circuit that coordinates with EI
2
OS, the counter can start EI
2
OS when
PPG interrupt occurs.
However, EI
2
OS is available only when other peripheral functions sharing the interrupt control register
(ICR) do not use interrupts. For example, when 16-bit PPG timer 0 uses EI
2
OS, interrupts of the output
compare channel 0 match must be disabled.
Table 13.5-2 16-bit PPG Timer Interrupts and EI
2
OS
Channel
Interrupt
number
Interrupt control register Vector table address
EI
2
OS
Register name Address Lower Middle Upper
16-bit PPG timer 0
*1
#14 (0E
H
)
ICR01
0000B1
H
FFFFC4
H
FFFFC5
H
FFFFC6
H
O
16-bit PPG timer 1
*2
#16 (10
H
)
ICR02
0000B2
H
FFFFBC
H
FFFFBD
H
FFFFBE
H
16-bit PPG timer 2
*3
#32 (20
H
)
ICR10
0000BA
H
FFFF7C
H
FFFF7D
H
FFFF7E
H
*1: The same interrupt control register as that for 16-bit PPG timer 0 is assigned to PWC timer 0.
*2: The same interrupt control register as that for 16-bit PPG timer 1 is assigned to 16-bit output compare channel 1 match.
*3: The same interrupt control register as that for 16-bit PPG timer 2 is assigned to 16-bit free-run timer zero detect.