Fujitsu MB90460 Series, Hardware Manual, Page: 227 / 739

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CHAPTER 10 TIME-BASE TIMER
10.2 Configuration of the Time-base Timer
The time-base timer consists of the following four blocks:
• Time-base timer counter
• Counter clear circuit
• Interval timer selector
• Time-base timer control register (TBTC)
■
Block Diagram of the Time-base Timer
Figure 10.2-1 shows the block diagram of the time-base timer.
Figure 10.2-1 Block Diagram of the Time-base Timer
●
Time-base timer counter
This 18-bit up counter uses the divide-by-two clock of the oscillation clock (HCLK) as the count clock.
●
Counter clear circuit
Used to clear the counter by writing "0" to the TBTC:TBR bit, by a power-on reset or by transition to stop
mode (LPMCR: STP = 1).
●
Interval timer selector
Selects one of four outputs of the time-base timer counter. An overflow of the selected bit becomes an
interrupt cause.
●
Time-base timer control register (TBTC)
Selects the interval, clears the counter, controls an interrupt request, and checks the status.
OF:Overflow
HCLK: O
s cill a tion clock
*1 : S witching of the m a chine clock from the o s cill a tion clock to the PLL clock
*2 : Interr u pt n u m b er
OF
OF
OF
Time- bas e
timer co u nter
Divide- b y
-two HCLK
Powe r-on re s et
S top mode s t a rt
Co u nter
cle a r circ u it
Interv a l
timer s elector
To w a tchdog timer
To the o s cill a tion
s etting time s elector
in the clock control
s ection
2
1
2
2
2
3
. . . . . .
2
8
2
9
2
10
2
11
2
12
2
1 3
2
14
2
15
2
16
2
17
2
1 8
OF
Co u nter cle a r
— — TBR TBC1 TBC0 —
TBIE TBOF
CK S CR: MC S = 1 to 0(*1)
Time- bas e timer
interrpt regi s ter (TBTC)
TBOF cle a r
TBOF s et
Time- bas e timer
interr u pt s ign a l
# 3 6 (24
H
)(*2)
OF
× × × × ×
×
× × ×
×
× × × ×