Fujitsu MB90460 Series, Hardware Manual, Page: 113 / 739

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CHAPTER 6 LOW POWER CONSUMPTION MODE
6.3 Low Power Consumption Mode Control Register (LPMCR)
The low power consumption mode control register (LPMCR) switches to or releases low
power consumption mode. It is also used to set the number of CPU clock pulses the
CPU is to be halted during CPU intermittent mode.
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Low Power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 shows the configuration of the low power consumption mode control register (LPMCR).
Figure 6.3-1 Configuration of the Low Power Consumption Mode Control Register (LPMCR)
Addre ss
0000A0
H
Initi a l v a l u e
00011000
B
(CK S CR) S TP S LP RE S V S PL R S T TMDX CG1 CG0
CG1
0 0 0 clock p u l s e (CPU clock = Peripher a l clock)
9 clock p u l s e s (CPU clock: Peripher a l clock = 1: 3 to 4 a pprox.)
17 clock p u l s e s (CPU clock: Peripher a l clock = 1: 5 to 6 a pprox.)
33 clock p u l s e s (CPU clock: Peripher a l clock = 1: 9 to 10 a pprox.)
0 1
1 0
1 1
CG0
CPU h a lt clock p u l s e s s election b it s
R S T
0 Gener a te s a n intern a l re s et s ign a l of 3 m a chine cycle s .
No ch a nge, no effect on oper a tion 1
Intern a l re s et s ign a l gener a tion b it
S PL
0 Ret a ined
High-imped a nce 1
Pin s t a te s etting b it (for time- bas e timer mode a nd s top mode)
S LP
0 No ch a nge, no effect on oper a tion
S witch to s leep mode 1
S leep b it
RE S V
1 m us t a lw a y s b e written to the s e b it s .
Re s erved b it
15 b it
W W R/W W W R/W R/W R/W
7 6 5 4 3 2 1 0
R/W: Re a d/write
W: Write-only
: Initi
a l v a l u e
TMDX
0 S witch to time- bas e timer mode
No ch a nge, no effect on oper a tion
1
Time- bas e timer b it
S TP
0 No ch a nge, no effect on oper a tion
S witch to s top mode
1
S top b it