Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 3 INTERRUPTS
3.3 Interrupt Control Registers (ICR)
The interrupt control registers are in the interrupt controller. Each interrupt control
register has a corresponding I/O that has an interrupt function. The interrupt control
registers have the following three functions:
• Setting an interrupt level for corresponding peripherals
• Selecting whether to use an ordinary interrupt or extended intelligent I/O service for
the corresponding peripherals
• Selecting the extended intelligent I/O service channel
Do not access an interrupt control register by using a read-modify-write (RMW)
instruction, as doing so causes a misoperation.
■
Interrupt Control Register (ICR)
Figure 3.3-1 shows an interrupt control register (ICR).
Figure 3.3-1 Interrupt Control Register (ICR)
Notes:
• ICS3 to ICS0 can only be enabled when you activate EI
2
OS. Set ISE bit to "1" if you activate
EI
2
OS. Otherwise, set ISE bit to "0". Any value can be set to ICS3 to ICS0 if you don’t activate
EI
2
OS.
• ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only.
<Additional information>
The extended intelligent I/O service channel select bits (ICR: ICS3 to ICS0) are valid for write
only. The extended intelligent I/O service status bits (ICR: S1, S0) are valid for read only. When
reading, "1" is returned from bit6, bit7/bit14, bit15 (ICS2, ICS3).
[bit10 to bit8, bit2 to bit0] IL0, IL1, and IL2 (interrupt level setting bits)
These bits are readable and writable, and specify the interrupt level of the corresponding internal
resources. Upon a reset, these bits are initialized to level 7 (no interrupt). Table 3.3-1 shows an interrupt
level setting bits and interrupt levels.
Interrupt control register
00000111
B
w hen reset
ISE IL2 IL1 IL0
15/7 bit
ICS1
ICS3 ICS2
or
S1
ICS0
or
S0
W W R/W R/W
14/6 13/5 12/4
11/3
10/2 9/1
8/0
R/W
R/W
* *
*: "1" is read al w ays. ICS1 and ICS0 are valid for w rite only. S1 and S0 are valid for read only.