Fujitsu MB90390 Series, Hardware Manual

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CHAPTER 21 400 kHz I
2
C INTERFACE
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Addressing Slaves
In master mode, after a start condition is generated the BB and TRX bits are set to "1" and the contents of
the IDAR register is sent in MSB first order. After address data is sent and an acknowledge signal was
received from the slave device, bit0 of the sent data (bit0 of the IDAR register after sending) is inverted and
stored in the TRX bit. Acknowledgement by the slave may be checked using the LRB bit in the IBSR
register. This procedure also applies to a repeated start condition.
In order to address a ten bit slave for write access, two bytes have to be sent. The first one is the ten bit
address header which consists of the bit sequence "1 1 1 1 0 A9 A8 0", it is followed by the second byte
containing the lower eight bits of the ten bit slave address (A7 - A0).
A ten bit slave is accessed for reading by sending the above byte sequence and generating a repeated start
condition (SCC bit in IBCR) followed by a ten bit address header with read access (1 1 1 1 0 A9 A8 1).
Summary of the address data bytes:
7 bit slave, write access: Start condition - A6 A5 A4 A3 A2 A1 A0 0.
7 bit slave, read access: Start condition - A6 A5 A4 A3 A2 A1 A0 1.
10 bit slave, write access: Start condition - 1 1 1 1 0 A9 A8 0 - A7 A6 A5 A4 A3 A2 A1 A0.
10 bit slave, read access: Start condition - 1 1 1 1 0 A9 A8 1 - A7 A6 A5 A4 A3 A2 A1 A0 - repeated start
- 1 1 1 1 0 A9 A8 1.
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Arbitration
During sending in master mode, if another master device is sending data at the same time, arbitration is
performed. If a device is sending the data value "1" and the data on the SDA line has an "L" level value, the
device is considered to have lost arbitration, and the AL bit is set to "1". Also, the AL bit is set to "1" if a
start condition is detected at the first bit of a data byte but the interface did not want to generate one or the
generation of a start or stop condition failed by some reason.
Arbitration loss detection clears both the MSS and TRX bit and immediately places the device in slave
mode so it is able to acknowledge if its own slave address is being sent.
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Acknowledgement
Acknowledge bits are sent from the receiver to the transmitter. The ACK bit in the IBCR register can be
used to select whether to send an acknowledgment when data bytes are received.
When data is send in slave mode (read access from another master), if no acknowledgement is received
from the master, the TRX bit is set to "0" and the device goes to receiving mode. This enables the master to
generate a stop condition as soon as the slave has released the SCL line.
In master mode, acknowledgement by the slave can be checked by reading the LRB bit in the IBSR
register.