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3. Details of hardware
MB86R11
Evaluation Board
MB86R11EVB Hardware Manual
3.2.
Base board
The AC adaptor is connected to this board, and it supplies power to each board.
The signal of the Display, Capture, and External Bus are connected to FPGA, and an enable control is
performed for the buffer of each resource according to the mode that the user set.
3.2.1.
FPGA
The FPGA of the Base board provides a selector function of Display and Capture and a buffer enable
control functions of each resource.
External Bus connects the following signals with FPGA:
lower 10 bits of address (A[11:1])
32 bits control signal (excluding the signal for NAND) of data
Table 3-14 FPGA
No.
Item
Model number
Manufacturer
Quantity
Remarks
1 FPGA
XC6SLX100-2FGG676C Xilinx
1 Spartan6
2
Writing connector
98424-G52-14ALF
FCI
1
2 rows, 14 poles
3 Configuration
ROM S25FL032P0XMFI011 SPANSION
1 32Mbit
3.2.2.
External Bus
The 256MB NAND-FLASH is connected to External Bus of the Base board.
To connect External Bus signals with customer's board, they are connected to the connector.
Refer to "4.3 Customer I/F" for detail.
Table 3-15 External Bus
No.
Item
Model number
Manufacturer
Quantity
Remarks
1 NAND-FLASH
MT29F2G08ABAEAWP MICRON
1 256MB (8bit
×
256Mbit)
