Fujitsu MB86617A Specification Sheet Download Page 11

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LSI S pecification

MB86617A

Rev.1.0

Fujitsu VLSI

Asynchronous Receive FIFO Extended Mode

Fig.3.1.3 Block Diagram - Asynchronous Receive FIFO Extended Mode

1394 Interface (Port 0)

TPA0

XTPA0

TPB0

XTPB0

TPBIAS0

1394 Interface (Port 1)

TPA1

XTPA1

TPB1

XTPB1

TPBIAS1

1394 Interface (Port 2)

TPA2

XTPA2

TPB2

XTPB2

TPBIAS2

PHY/

LINK

Layer

Control

Circuit

CP IC

Interface

FIFO

(2KByte)

FIFO

(2KByte

)

Asynch Transmit

Exclusive FIFO

(256 byte)

Asynch Transmit

Exclusive FIFO

(256 byte)

TSP IC Interface

FIFO

(2KByte)

FIFO

(2KByte)

Asynch Transmit

Packet Process

Host Interface

Asynch Transmit

Packet Process

Data Bridge

Summary of Contents for MB86617A

Page 1: ...LSI Specification MB86617A Rev 1 0 Fujitsu VLSI i IEEE1394 Serial Bus Controller for DTV MB86617A LSI Specification Rev 1 0 August 16 2001 ...

Page 2: ...OL CIRCUIT 7 LINK LAYER CONTROL CIRCUIT 7 TSP IC INTERFACE 7 CP IC INTERFACE 7 DATA BRIDGE 7 CHAPTER 4 PIN ASSIGN MENT 8 4 1 PIN ASSIGNMENT 9 4 2 CORRESPONDING TABLE OF MB86617A PIN 10 4 3 OUTLINE DRAWING OF PACKAGE 11 CHAPTER 5 PIN FUNCTION 12 5 1 IEEE1394 INTERFACE 13 5 2 ISOCHRONOUS INTERFACE 14 5 4 MPU INTERFACE 16 5 5 OTHER PINS 17 5 6 POWER GND PIN 18 CHAPTER 6 INTERNAL REGISTER 19 CHAPTER 7...

Page 3: ...SMIT INFORMATION SETTING REGISTER 1 A 48 7 16 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 2 A 49 7 17 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 3 B 50 7 18 DATA BRIDGE TRANSMIT INFORMATION SETTING REGISTER 4 B 51 7 19 DATA BRIDGE RECEIVE INFORMATION SETTING REGISTER 52 7 20 TRANSMIT PACKET LINK SPLIT SETTING REGISTER 53 7 21 LATE PACKET DECISION RANGE SETTING REGISTER A 55 7 22 LATE ...

Page 4: ... 00 READ 83 8 3 PHYSICAL REGISTER 01 READ WRITE 84 8 4 PHYSICAL REGISTER 02 READ 85 8 5 PHYSICAL REGISTER 03 READ 86 8 6 PHYSICAL REGISTER 04 READ WRITE 87 8 7 PHYSICAL REGISTER 05 READ WRITE 88 8 8 PHYSICAL REGISTER 07 08 09 READ 90 8 9 PHYSICAL REGISTER 0A 0B 0C READ WRITE 91 8 10 PHYSICAL REGISTER 0D 0E 0F READ WRITE 92 8 11 PHYSICAL REGISTER 10 READ 93 8 12 PHYSICAL REGISTER 11 12 13 READ 94 8...

Page 5: ...Packet Receive at Bus Reset Process 115 11 2 2 Self ID Packet Receive after Transmitting Ping Packet Ping 118 11 3 ASYNCHRONOUS PACKET TRANSMITTING 120 11 4 ASYNCHRONOUS PACKET RECEIVING 122 11 5 ISOCHRONOUS PACKET TRANSMITTING 125 11 6 ISOCHRONOUS PACKET RECEIVING 128 CHAPTER 12 SYSTEM CONFIGURATION 130 12 1 RECOMMENDED CONNECTION FOR 1934 PORT FOR ONE PORT 131 12 2 RECOMMENDED CONNECTION FOR CAB...

Page 6: ...ironment differential transceiver and comparator and the transfer data rate supports S400 MB86617A integrates PHY and LINK layers into single chip and plans for degression of component side product and saving power consumption MB86617A has two exclusive ports one is the combined use for receiving a message of interface for DV for MPEG2 and DSS data transfer and performs isolating and packeting of ...

Page 7: ... On chip PLL corresponding to Crystal Osci llator generate internal clock 4K Byte X 2 channels Isochronous transmit and receive data buffer 256Byte Asynchronous exclusive buffer for transmit receive Auto isolating and packetingfor received header and data of packet Two exclusive ports for Isochronous transfer 8 bit bus Loading interface with copy protection LSI 8 bits I O Generating and Checking F...

Page 8: ...LSI S pecification MB86617A Rev 1 0 Fujitsu VLSI 3 Chapter 3 Chip Block This chapter explains the MB86617A block diagram and the function of each block 3 1 Block Diagram 3 2 FunctionofEachBlock ...

Page 9: ...PA0 TPB0 XTPB0 TPBIAS0 1394 Interface Port 1 TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface Port 2 TPA2 XTPA2 TPB2 XTPB2 TPBIAS2 PHY LINK Layer Control Circuit CP IC Interface FIFO 2KByte FIFO 2KByte Asynch Transmit Exclusive FIFO 256 byte Asynch Transmit Exclusive FIFO 256 byte TSP IC Interface FIFO 2KByte FIFO 2KByte AsynchTransmit Packet Process Host Interface AsynchTransmit Packet Process Data B...

Page 10: ... XTPB0 TPBIAS0 1394 Interface Port 1 TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface Port 2 TPA2 XTPA2 TPB2 XTPB2 TPBIAS2 PHY LINK Layer Control Circuit CP IC Interface FIFO 2KByte FIFO 2KByte Asynch Transmit Exclusive FIFO 256 byte Asynch Transmit Exclusive FIFO 256 byte TSP IC Interface FIFO 2KByte FIFO 2KByte AsynchTransmit PacketProcess Host Interface AsynchTransmit PacketProcess Data Bridge ...

Page 11: ...TPB0 TPBIAS0 1394 Interface Port 1 TPA1 XTPA1 TPB1 XTPB1 TPBIAS1 1394 Interface Port 2 TPA2 XTPA2 TPB2 XTPB2 TPBIAS2 PHY LINK Layer Control Circuit CP IC Interface FIFO 2KByte FIFO 2KByte Asynch Transmit Exclusive FIFO 256 byte Asynch Transmit Exclusive FIFO 256 byte TSP IC Interface FIFO 2KByte FIFO 2KByte AsynchTransmit Packet Process Host Interface AsynchTransmit Packet Process Data Bridge ...

Page 12: ...SP IC Interface has two exclusive ports with the following functions for transmitting receiving TSP IC MPEG2 TS and DSS data and receiving DV data Adds time stamp to both MPEG2 TS and DSS data Outputs received data just when the value of time stamp SPH and cycle timer is matched with eachother Integrated transmit receive dual purpose FIFO for transferring Isochronous by 2K byte X 2 channels CP IC ...

Page 13: ...86617A Rev 1 0 Fujitsu VLSI 8 Chapter 4 Pin Assignment This chapter explains the pin assignment and table of pin function of MB86617A 4 1 Pin Assignment 4 2 Corresponding Table of MB86617A Pin 4 3 Outline Drawing of Package ...

Page 14: ...A TSCGMSA TSSYNCA TSCLKA VSS VDD VSS VDD VSS VDD XRESET MODE1 MODE0 XCS XWR XDS XRD R XW ALE XINT DREQ XDACK VDD VSS D15 D14 D13 D12 D11 D10 D9 D8 VDD VSS AD7 AD6 AD5 AD4 AD3 AD2 AD1 D0 TEST1 TEST2 VSS XI VDD XO AVSS AVDD FIL RF AVSS AVDD RO CPS SELTSPA DSSCLKA VDD VSS TSCLKB TSSYNCB TSCGMSB TSVALB TSDB7 TSDB6 TSDB5 TSDB4 VDD VSS TSDB3 TSDB2 TSDB1 TSDB0 IERRB SELIOB SELTSPB DSSCLKB VDD VSS TEST3 T...

Page 15: ...DD 105 VDD 149 I O TSDB1 18 I O D10 62 AVSS 106 VSS 150 I O TSDB0 19 I O D9 63 AVSS 107 151 O IERRB 20 I O D8 64 AVDD 108 152 O SELIOB 21 VDD 65 I O XTPB0 109 153 O SELTSPB 22 VSS 66 I O TPB0 110 154 I DSSCLKB 23 I O AD7 67 I O XTPA0 111 155 VDD 24 I O AD6 68 I O TPA0 112 156 VSS 25 I O AD5 69 O TPBIAS0 113 157 I O TEST3 26 I O AD4 70 AVDD 114 158 I O TEST4 27 I O AD3 71 AVSS 115 VDD 159 O XFP 28 ...

Page 16: ...LSI S pecification MB86617A Rev 1 0 Fujitsu VLSI 11 4 3 Outline Drawing of Package This section shows the outline drawing of MB86617A package LQFP 176 ...

Page 17: ...n MB86617A Rev 1 0 Fujitsu VLSI 12 Chapter 5 Pin Function This chapter explains the MB86617A pin function 5 1 IEEE1394 Interface 5 2 Isochronous TSP IC DV IC Interface 5 4 MPU Interface 5 5 Other Pins 5 6 Power GND Pin ...

Page 18: ...able port 1 XTPA1 I O I O pin of TPA minus signal on cable port 1 TPB1 I O I O pin of TPB plus signal on cable port 1 XTPB1 I O I O pin of TPB minus signal on cable port 1 TPA2 I O I O pin of TPA plus signal on cable port 2 XTPA2 I O I O pin of TPA minus signal on cable port 2 TPB2 I O I O pin of TPB plus signal on cable port 2 XTPB2 I O I O pin of TPB minus signal on cable port 2 TPBIAS0 O Output...

Page 19: ...ting effective data period of TS packet on port B H active signal TSSYNCB I O Input Output pin for indicating leading data of TS packet on port B H active signal TSCLKB I O On transmitting sync clock input pin for input data of TS packet On receiving sync clock output pin for output data of TS packet switchable either 6 144MHz or 3 072MHz TSDB7 0 I O I O pin for TS packet data on port B TSCGMSB I ...

Page 20: ...5 IERRA O Output pin for noticing error of receive data on port A H active signal IERRB O Output pin for noticing error of receive data on port B H active signal DSSCLKA I Clock input pin for DSS data 27MHz DSSCLKB I Clock input pin for DSS data 27MHz ...

Page 21: ...put pin for this device XRD R W I 80 system mode read out strobe input pin for this device 68 system mode input pin for controlling read out write for this device XWR XDS I 80 system mode strobe input pin for writing into this device 68 system mode input pin of XDS signal to be output with data bus in available ALE I Input pin of ALE signal to be output with its address in available when selecting...

Page 22: ...through 5 1kΩ register CPS I Power supply input pin from IEEE1394 cable Detect cable supply power 0 to 33V requiring of lowering dividing voltage PMODE I Criterion pin for inputting power L input operate with power supplying through IEEE1394 cable H input operate with system power PWR3 1 I Setting pin got POWER_CLASS of Self ID packet to be transmitted when operating with supply power through cabl...

Page 23: ...on MB86617A Rev 1 0 Fujitsu VLSI 18 5 6 Power GND Pin This section explains the power GND pin Signal Name I O Function VDD 3 3V digital power pin VSS Digital ground pin AVDD 3 3V analog power pin AVSS Analog ground pin ...

Page 24: ...wledge 0C A bufferdata port transmit A bufferdata port receive 0E reserved reserved 10 TSP transmit information setting A TSP transmit information setting A 12 TSP transmit information setting B TSP transmit information setting B 14 transmit offset setting A upper transmit offset setting A upper 16 transmit offset setting A lower transmit offset setting A lower 18 transmit offset setting B upper t...

Page 25: ...st significant receive DSS packet header setting B least significant 32 reserved TSP status 34 data bridge transmit information setting 1 A data bridge transmit information setting 1 A 36 data bridge transmit information setting 2 A data bridge transmit information setting 2 A 38 data bridge transmit information setting 3 B data bridge transmit information setting 3 B 3A data bridge transmit infor...

Page 26: ...or upper 5C reserved cycle time monitor lower 5E reserved Ping time monitor 60 PHY LINK register address setting PHY LINK register address setting 62 PHY LINK register access port PHY LINK register access port 64 reserved Revision indicate register upper 66 reserved Revision indicate register lower 68 reserved reserved 6A reserved reserved 6C reserved reserved 6E reserved reserved 70 reserved rese...

Page 27: ...ransmit EMI OE setting transmit EMI OE setting 88 reserved reserved 8A reserved reserved 8C reserved reserved 8E reserved reserved 90 reserved reserved 92 reserved reserved 94 reserved reserved 96 reserved reserved 98 reserved reserved 9A reserved reserved 9C reserved reserved 9E reserved reserved A0 reserved reserved A2 reserved reserved A4 reserved reserved A6 reserved reserved A8 reserved reser...

Page 28: ...erved BA reserved reserved BC reserved reserved BE reserved reserved C0 reserved reserved C2 reserved reserved C4 reserved reserved C6 reserved reserved C8 reserved reserved CA reserved reserved CC reserved reserved CE reserved reserved D0 reserved reserved D2 reserved reserved D4 reserved reserved D6 reserved reserved D8 reserved reserved DA reserved reserved DC reserved reserved DE reserved rese...

Page 29: ...erved E2 reserved reserved E4 reserved reserved E6 reserved reserved E8 reserved reserved EA reserved reserved EC reserved reserved EE reserved reserved F0 reserved reserved F2 reserved reserved F4 reserved reserved F6 reserved reserved F8 reserved reserved FA reserved reserved FC reserved reserved FE reserved reserved ...

Page 30: ...fset Setting Register B 7 11 TSP Receive Information Setting Register 7 12 Transmit DSS Packet Header Setting Register A 7 13 Transmit DSS Packet Header Setting Register B 7 14 TSP Status Register 7 15 Data Bridge Transmit Information Setting Register 1 A 7 16 Data Bridge Transmit Information Setting Register 2 A 7 17 Data Bridge Transmit Information SettingRegister3 B 7 18 Data Bridge Transmit In...

Page 31: ...A 7 29 Data Bridge Transmit Receive Status Register B 7 30 Isochronous channel monitor Register 7 31 cycle timer monitorIndicateRegister 7 32 Ping time monitor Register 7 33 PHY LINK Register Address Setting Register 7 34 PHY LINK Register Access Port 7 35 Revision Indicate Register 7 36 Transmit CGMS TSCH Indicate Register A 7 37 Transmit CGMS TS CH Indicate Register B 7 38 Transmit CGMS TSCH Ind...

Page 32: ...F and data bridge when PMODE input terminal is in H 0 Deletes Self ID packet in spite of receiving it during bus reset 9 s ID store Note 1 Read Write 1 In case of receiving Self ID packet during bus reset process this bit stores 512 byte at maximum accompanying with both Asynchronous receive FIFO and Asynchronous transmit FIFO 0 Enable CP IC interface Needs external CP IC 8 Cp_through Read Write 1...

Page 33: ...t with Asyn FIFO sel bit3 1 2 send rec Read Write 1 Uses 2K byte FIFO for Asynchronous receive with Asyn FIFO sel bit3 1 0 Activates TSP IC I F terminal output 1 TSP stand by Read Write 1 Disables TSP IC I F terminal output and brings it in high impedance status 0 Activates CP I F terminal output 0 CP stand by Read Write 0 Disables CP I F terminal output and brings it in high impedance status Note...

Page 34: ...ran ready Read 1 Indicates that bus reset is completed and forced sleep is not being executed and transmit receive of packet is available 0 Indicates that packet transmit is not being executed or in the process of packet receive addressed to this node 13 tran busy Read 1 Indicates that packet transmit is being executed or in the process of packet receive addressed to this node 0 Indicates that Iso...

Page 35: ...busy mode 2 recv busy Note 2 Read 1 Indicates that packet receive is in busy mode due to receipt of Asynchronous packet and self ID packet 0 Indicates that node is not the cycle master now 1 cmstr Read 1 Node is the cycle master now 0 Interrupt indicate register does not have interrupt 0 INT Read 1 Interrupt indicate register has interrupt Note 1 IEEE1394 block is in internal reset status until in...

Page 36: ... 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 04h R W Instruction code operand Initial Value 00h 00h BIT Bit Name Action Value Function 15 8 instruction code Read Write Specify each instruction code 7 0 operand Read Write Specify required operand for each instruction code Write 0 into all bits for instructions without operand Note Before writing in instructio...

Page 37: ...Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Interrupt factor 06h W interrupt mask R Interrupt factor 08h W interrupt mask Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BIT Bit Name Action Value Function 0 Indicate that interrupt factors are not generated interrupt facto r Read 1 Indicate that interrupt factors are generated After reading out thi...

Page 38: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0Ah R Receive ack code Receive ack parity Initial Value 0 0 0 0 0 0 0 0 0 h 0h BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 4 Receive Acknowledge co de Read Indicate code of received Acknowledge packet addressed to it MSB bit7 LSB bit5 3 0 Receive Acknowledge par ity Read Indicate parity of received Acknowledge packet addressed to ...

Page 39: ...E1394 packet data in the order written in MSB 1ST write AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R ASYNC Receive Specific Buffer Data 0Ch W ASYNC Transmit Specific Buffer Data Initial Value Undefined BIT Bit Name Action Value Function ASYNC Receive Specific Buffer Data Read Read out port of Asynchronous receive specific buffer MSB...

Page 40: ... Automatically clears when transmit process is started with bridge Ach after setting at 1 15 Tx start A Read Write 1 Starts transmit processing with bridge Ach 0 Automatically clears when transmit process is stopped by bridge Ach after setting at 1 14 Tx end A Read Write 1 Stops transmit process by bridge Ach 0 Outputs L to SELTSPA output terminal 13 Tx select A Read Write 1 Outputs H to SELTSPA o...

Page 41: ... EMI information to be output to CP IC Valid only when EMI select A bit4 is 1 MSB bit3 LSB bit2 0 Does not insert internal 27 MHz counter value to System clock count ran ge of DSS packet header 1 27M count A Read Write 1 Inserts internal 27 MHz counter value to System clock count range of DSS packet header 0 Does not mask port A input of TSP IC interface Read in input data from port A at transmit ...

Page 42: ...utomatically clears when transmit process is started with bridge Bch after setting at 1 15 Tx start B Read Write 1 Starts transmit process with bridge Bch 0 Automatically clears when transmit process is stopped by bridge Bch after setting at 1 14 Tx end B Read Write 1 Stops transmit process by bridge Bch 0 Outputs L to SELTSPB output terminal 13 Tx select B Read Write 1 Outputs H to SELTSPB output...

Page 43: ...te Set EMI information to be output to CP IC Valid only when EMI select A bit4 is 1 MSB bit3 LSB bit2 0 Does not insert internal 27 MHz counter to System clock count range of DSS packet header 1 27M count B Read Write 1 Inserts internal 27 MHz counter to System clock count range of DSS packet header 0 Does not mask port B input of TSP IC interface Reads in input data from port A at transmit 0 port...

Page 44: ... byte of source packet from TSP IC AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 14h R W reserved transmit offset A high 16h R W transmit offset A low Initial Value 0000 h BIT Bit Name Action Value Function Read Always indicate 0 15 4 high reserved Write Always write in 0 3 0 high 15 12 low Set value to be added to cycle count range of...

Page 45: ...t byte of source packet from TSP IC AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 18h R W reserved transmit offset B high 1Ah R W transmit offset B low Initial Value 0000 h BIT Bit Name Action Value Function Read Always indicate 0 15 4 high reserved Write Always write in 0 3 0 high 15 12 low Set value to be added to cycle count range o...

Page 46: ... received by bridge Bch to port A of TSP IC I F 14 TV1B Read Write 1 Outputs packet received by bridge Bch to port A of TSP IC I F Read Always indicates 0 13 12 reserved Write Always write in 0 0 Outputs DSS packet received by bridge Bch with DSS packet header attached to TSP IC in unit of 140 byte 11 output DSS size B Read Write 1 Outputs DSS packet received by bridge Bch without attachment of DS...

Page 47: ...d by bridge Ach to TSP IC in unit of 130 byte Removed DSS packet header is stored at receive DSS packet header indicate register A 0 Outputs received data to TSP IC in synchronization with 6 144 MHz TSCLK 2 TCLKSL Read Write 1 Outputs received data to TSP IC in synchronization with 3 072 MHz TSCLK 0 Outputs to port A when TSCMP bit0 is 1 1 CMPSEL Read Write 1 Outputs to port B when TSCMP bit0 is 1...

Page 48: ...Port A TSP IC I F Port B 0 0 0 1 0 0 Processing Ach Receive data 0 0 1 0 0 0 Processing Ach Receive data 0 1 0 0 0 0 Processing Bch Receive data 1ch receive 1 0 0 0 0 0 Processing Bch Receive data 1 0 0 1 0 0 Processing Ach Receive data Processing Bch Receive data 0 1 1 0 0 0 Processing Bch Receive data Processing Ach Receive data 0 0 0 0 0 1 Processing Ach Bc h Receive data 2ch receive 0 0 0 0 1 ...

Page 49: ... A low Tx E F A reserved R reserved 22h W reserved R reserved 24h W reserved R reserved 26h W reserved Initial Value 0000 h BIT Bit Name Active Value Function Rx SIF A Read Indicates SIF range of received DSS packet header 15 1Eh Tx SIF A Write Write in SIF range of transmits DSS packet header Rx System clock count A Read Indicate System clock count range of received DSS packet header MSB 1Eh bit1...

Page 50: ...e B low Tx E F B reserved R reserved 2Ch W reserved R reserved 2Eh W reserved R reserved 30h W reserved Initial Value 0000 h BIT Bit Name Action Value Function Rx SIF B Read Indicates SIF range of receive DSS packet header 15 28h Tx SIF B Write Write in SIF range of transmit DSS packet header Rx System clock count B Read Indicate System clock count range of receive DSS packet header MSB 28h bit14 ...

Page 51: ... TSCH classification ID input from port B of TSP IC I F is not consistent with TSCH classification ID 10h bit12 to 7 set TS ID A or 12h bit12 to 7 set TS ID B to be stored to FIFO Clears to 0 by lead of this register 0 Indicates that synchronization byte of received MPEG2 TS input from CP IC by bridge Bch is 47h 13 no 47h B Read 1 Indicates that synchronization byte of received MPEG2 TS input from...

Page 52: ...Indicates that synchronization byte of received MPEG2 TS input from CP IC by bridge Bch is 47h 5 no 47h A Read 1 Indicates that synchronization byte of received MPEG2 TS input from CP IC by bridge Bch is not 47h Clears to 0 by lead of this register 0 Indicates that FIFO on TSP IC I F side of bridge Ach is not full 4 TSP FIFO full A Read 1 Indicates that FIFO on TSP IC I F side of bridge Ach is ful...

Page 53: ...9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 34h R W Tx SID A Tx DBS A Tx FN A Initial Value 00 h 00 h 00 b BIT Bit Name Action Value Function 15 10 Tx SID A Read Write Writein SID range of transmit CIP header MSB bit15 LSB bit10 9 2 Tx DBS A Read Write Writein DBS range of transmit CIP header MSB bit9 LSB bit2 MPEG2 TS at transmit 00000110 b DSS at transmit 00001001 b 1 0 Tx FN A Read ...

Page 54: ...x TSF A Tx channel A Tx speed A Initial Value 00 h 0 00 h 00 b 0 BIT Bit Name Action Value Function 15 10 Tx FMT A Read Write Writein FMT range of transmit CIP header MSB bit15 LSB bit10 MPEG2 TS at transmit 100000 b DSS at transmit 100001 b 9 Tx TSF A Read Write Writein TSF range of transmitsCIP header 8 3 Tx channel A Read Write Write in channel range of transmit Isochronous packet header MSB bi...

Page 55: ...9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 38h R W Tx SID B Tx DBS B Tx FN B Initial Value 00 h 00 h 00 b BIT Bit Name Action Value Function 15 10 Tx SID B Read Write Writein SID range of transmit CIP header MSB bit15 LSB bit10 9 2 Tx DBS B Read Write Writein DBS range of transmit CIP header MSB bit9 LSB bit2 MPEG2 TS at transmit 00000110 b DSS at transmit 00001001 b 1 0 Tx FN B Read ...

Page 56: ...Tx TSF B Tx channel B Tx speed B Initial Value 00 h 0 00 h 00 b 0 BIT Bit Name Action Value Function 15 10 Tx FMT B Read Write Writein FMT range of transmit CIP header MSB bit15 LSB bit10 MPEG2 TS at transmit 100000 b DSS at transmit 100001 b 9 Tx TSF B Read Write Writein TSF range of transmit CIP header 8 3 Tx channel B Read Write Writein channel range of transmit Isochronous packet header MSB bi...

Page 57: ...start B Read Write 1 Executes receive process by bridge Bch 0 Automatically clears when receive process is stopped by bridge Bch after setting at 1 14 Rx end B Read Write 1 Stops receive process by bridge Bch 13 8 Rx channel B Read Write Write in Isochronous packet channel to be received by bridge Bch MSB bit8 LSB bit3 0 Automatically clears when receive process is executed by bridge Ach after set...

Page 58: ...ronous packet header Valid with o e select B bit15 setting value 1 and reads in this setting value to transmit Isochronous packet header 0 Executes 2SP combined transmission as FIFO NFULL operation when setting of 2SP separated transmission or combined transmission for less than 2SP With more than 3 SP executes according to setting 13 NF5SPB Read Write 1 Executes 5 SP combined transmission at FIFO...

Page 59: ...te in number of links for source packet processed by bridge Ach Note SPQ 2 0 Please specify link number of source packet Valid setting values are 0 5 Processes assuming there are no settings from microcomputer during 0 setting When 6 7 are set it is regarded to be 5 source packet link DBQ 1 0 Please specify split number of source packet 00 No setting from microcomputer 01 2 splits 10 4 splits 11 8...

Page 60: ...et decision is performed by comparing the time difference between SPH Source Packet Header and CTR Cycle Time Monitor Transmit Packet is transmitted normally when calculation result of SPH minus CTR for source packet transmitted from Bridhe Ach is within the late range A 0000 h If it is out of range Late packet process is performed The packet concerned is deleted and transmit late is reported Set ...

Page 61: ...et decision is performed by comparing the time difference between SPH Source Packet Header and CTR Cycle Time Monitor Transmit Packet is transmitted normally when calculation result of SPH minus CTR for source packet transmitted from Bridhe Bch is within the late range B 0000 h If it is out of range Late packet process is performed The packet concerned is deleted and transmit late is reported Set ...

Page 62: ...it 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 44h R Rx EMI A Rx o e A Rx SID A Initial Value 0 0 0 0 0 0 0 00 b 0 00 h BIT Bit Name Action Value Function 15 9 reserved Read Always indicate 0 8 7 Rx EMI A Read Indicate EMI range of receive Isochronous packet header MSB bit8 LSB bit7 6 Rx o e A Read Indicates odd even range of receive Isochronous packet header 5 0 R...

Page 63: ...Bit 3 Bit 2 Bit 1 Bit 0 46h R Rx FMT A Rx 56 A Rx STYPE A Initial Value 0 0 0 0 3F 0 00 h BIT Bit Name Action Value Function 15 12 reserved Read Always indicate 0 11 6 Rx FMT A Read Indicate FMT range of receive Isochronous packet CIP header MSB bit11 LSB bit6 5 Rx 56 A Read Indicates 50 60 range of receive Isochronous packet CIP header when receiving DV Indicates TSF range of receive Isochronous ...

Page 64: ...it 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 48h R Rx EMI B Rx o e B Rx SID B Initial Value 0 0 0 0 0 0 0 00 b 0 00 h BIT Bit Name Action Value Function 15 9 reserved Read Always indicate 0 8 7 Rx EMI B Read Indicate EMI range of receive Isochronous packet header MSB bit8 LSB bit7 6 Rx o e B Read Indicates odd even range of receive Isochronous packet header 5 0 R...

Page 65: ...Bit 3 Bit 2 Bit 1 Bit 0 4Ah R Rx FMT B Rx 56 B Rx STYPE B Initial value 0 0 0 0 3F 0 00 h BIT Bit Name Action Value Function 15 12 reserved Read Always indicate 0 11 6 Rx FMT B Read Indicate FMT range of receive Isochronous packet CIP header MSB bit11 LSB bit6 5 Rx 56 B Read Indicates 50 60 range of receive Isochronous packet CIP header when receiving DV Indicates TSF range of receive Isochronous ...

Page 66: ...te 1 Resets FIFO on TSP IC I F side of bridge Bch 0 Releases FIFO reset on LINK I F side of bridge Bch 13 resetBRG FIFO B Read Write 1 Resets FIFO on LINK I F side of bridge Bch Read Always indicate 0 12 8 reserved Write Always write in 0 0 Releases forced reset of bridge Ach 7 reset A Read Write 1 Execute forced reset of bridge Ach 0 Releases FIFO reset on TSP IC I F side of bridge Ach 6 reset TS...

Page 67: ...ot in the process of receive Indicates 0 when Rx end A 3Ch bit6 is set at 1 and receive process is stopped 14 Rx busy A Read 1 Indicates that bridge Ach is in the process of receive Indicates 1 when Rx start A 3Ch bit7 is set at 1 and receive process is started 0 Indicates that Isochronous packet received after starting receive process is not the first packet received 13 Rx 1STP A Read 1 Indicates...

Page 68: ... range of CIP header for received Isochronous packet is 0 6 Rx 56 err A Read 1 Indicates that 50 60 range of CIP header of received Isochronous packet is 1 Clears to 0 by lead of this register 0 Indicates that STYPE range of CIP hea der of received Isochronous packet is 00000 or 00001 5 Rx stype err A Read 1 Indicates that STYPE range of CIP header of received Isochronous packet is other than 0000...

Page 69: ...by lead of this register 0 Indicates that FMT range of CIP header of received Isochronous packet is the value allowed to be received at DV EN DSS EN or TS EN 1Ch bit10 to 8 DV 00000 MPEG2 10000 or DSS 100001 0 Rx FMT err A Read 1 Indicates that FMT range of CIP header of received Isochronous packet is other than the value allowed to be received at DV EN DSS EN or TS EN 1Ch bit10 to 8 DV 00000 MPEG...

Page 70: ...ot in the process of receive Indicates 0 when Rx end B 3Ch bit14 is set at 1 and receive process is stopped 14 Rx busy B Read 1 Indicates that bridge Bch is in the process of receive Indicates 1 when Rx start B 3Ch bit15 is set at 1 and receive process is started 0 Indicates that received Isochronous packet after starting receive process is not the first receive packet 13 Rx 1STP B Read 1 Indicate...

Page 71: ...0 range of CIP header of received Isochronous packet is 0 6 Rx 56 err B Read 1 Indicates that 50 60 range of CIP header of received Isochronous packet is 1 Clears to 0 by lead of this register 0 Indicates that STYPE range of CIP header of received Isochronous packet is 00000 or 00001 5 Rx stype err B Read 1 Indicates that STYPE range of CIP header of received Isochronous packet is other than 00000...

Page 72: ... by lead of this register 0 Indicates that FMT range of CIP header of received Isochronous packet is the value allowed to be received at DV EN DSS EN or TS EN 1Ch bit10 to 8 DV 00000 MPEG2 10000 or DSS 100001 0 Rx FMT err B Read 1 Indicates that FMT range of CIP header of received Isochronous packet is other than the value allowed to be received at DV EN DSS EN or TS EN 1Ch bit10 to 8 DV 00000 MPE...

Page 73: ... Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 52h R Isochronous channel monitor1 54h R Isochronous channel monitor2 56h R Isochronous channel monitor3 58h R Isochronous channel monitor4 Initial Value 0000 h BIT Bit Name Action Value Function 15 0 Isochronous channel monitor Read Indicate that 1 at Bit corresponding to channel number of Isochronous packet flowing through 1394 bus 52h bit15 0 channel0 channel15 54...

Page 74: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5Ah R cycle timer monitor hi 5Ch R cycle timer monitor lo Initial Value 0000 h BIT Bit Name Action Value Function 15 0 cycle timer m onitor Read Indicate value of built in cycle timer register MSB bit15 LSB bit0 Note This register latches the lower word 5A h by reading out lower word 5Ch and releases latch by reading out upper word To read out this register ma...

Page 75: ...ceiving response packet to the request AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5Eh R Ping time monitor Initial Value 0000 h BIT Bit Name Action Value Function 15 0 Ping time monitor Read Indicate time period from transmitting request packet to receiving response packet to the request Counts by 20ns unit MSB bit15 LSB bit0 ...

Page 76: ...ndicated with address set by this register can be accessed from PHY LINK register access port AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 60h R W phy link addr Initial Value 0 0 0 0 0 0 0 0 0 00 h BIT Bit Name Action Value Function Read Always indicate 0 15 7 reserved Write Always write in 0 6 0 phy link addr Read Write Set address o...

Page 77: ...rom this port AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 62h R W phy link data Initial Value 0000 h BIT Bit Name Action Value Function Read Indicates PHY LINK register contents defined by address set by PHY LINK register address setting register MSB 15 LSB 0 15 0 phy link data Write Executes write in the process of register defined ...

Page 78: ...gister that indicates chip revision of this LSI AD R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 64h Revision code hi 66h R Revision code lo Initial Value Fixed BIT Bit Name Action Value Function 15 0 Revision code Read Indicate Revision code MSB bit15 LSB bit0 ...

Page 79: ...A 1 TSCHA 1 Initial Value 00 b 00 h 00 b 00 h BIT Bit Name Action Value Function 15 14 CGMSA 2 Read Indicates CGMS information for source packet indicated in TSCHA 2 bit13 to 8 MSB bit15 LSB bit14 13 8 TSCHA 2 Read Indicates if ID of TS type for source packet input from port A at TSP IC I F is different from that in low bit TSCHA 1 MSB bit13 LSB bit8 7 6 CGMSA 1 Read Indicates CGMS information for...

Page 80: ...B 1 TSCHB 1 Initial Value 00 b 00 h 00 b 00 h BIT Bit Name Action Value Function 15 14 CGMSB 2 Read Indicates CGMS information for source packet indicated in TSCHB 2 bit13 to 8 MSB bit15 LSB bit14 13 8 TSCHB 2 Read Indicates if ID of TS type for source packet input from port B at TSP IC I F is different from that in low bit TSCHB 1 MSB bit13 LSB bit8 7 6 CGMSB 1 Read Indicates CGMS information for...

Page 81: ...packet indicated in CGMSB 1 and TSCHB 1 82h bit7 to 0 was finally input from port B at TSP IC I F Read 1 Indicates that the packet indicated in CGMSB 2 and TSCHB 2 82h bit15 to 8 was finally input from port B at TSP IC I F 10 Act TSCHB Write Clears to 0 by writing 1 0 Indicates that the value indicated in CGMSB 2 and TSCHB 2 82h bit15 to 8 is invalid Read 1 Indicates that the value indicated in CG...

Page 82: ...from port A at TSP IC I F 2 act TSCHA Write Clears to 0 by writing 1 0 Indicates that the value indicated in CGMSA 2 and TSCHA 2 80h bit15 to 8 is invalid Read 1 Indicates that the value indicated in CGMSA 2 and TSCHA 2 80h bit15 to 8 is valid 1 vld TSCHA 2 Write Clears to 0 by writing 1 0 Indicates that the value indicated in CGMSA 1 and TSCHA 1 80h bit7 to 0 is invalid Read 1 Indicates that the ...

Page 83: ...alid data is transmitted after starting transmission 14 13 IPH EMI B Read Write Set EMI information which are set in IPH of empty packet transmitted from bridge Bch Valid only when IPH select B bit15 is set to 1 MSB bit14 LSB bit13 EMI information after transmitting valid data depends on the setting of EMI select B 12h bit4 12 IPH OE B Read Write Set Odd Even value which is set in IPH of empty pac...

Page 84: ...7 is set to 1 MSB bit6 LSB bit5 EMI information after transmitting valid data depends on the setting of EMI select A 10h bit4 4 IPH OE A Read Write Set Odd Even value which is set in IPH of empty packet transmitted from bridge Ach Valid only when IPH select A bit7 is set to 1 EMI information after transmitting valid data depends on the setting of o e select A 3Eh bit8 Read Always indicate 0 3 0 re...

Page 85: ... in detail 8 1 PHY LINKRegisterTable 8 2 Physical Register 00 8 3 Physical Register 01 8 4 Physical Register 02 8 5 Physical Register 03 8 6 Physical Register 04 8 7 Physical Register 05 8 8 PhysicalRegister 07 08 09 8 9 Physical Register 0A 0B 0C 8 10 Physical Register 0D 0E 0F 8 11 Physical Register 10 8 12 Physical Register 11 12 13 8 13 Physical Register 14 15 16 8 14 PhysicalRegister 17 18 19...

Page 86: ... 0Ah Physical register 05 0Ch reserved Physical r egister 07 0Eh reserved Physical register 08 10h reserved Physical register 09 12h Physical register 0A 14h Physical register 0B 16h Physical register 0C 18h Physical register 0D 1Ah Physical register 0E 1Ch Physical register 0F 1Dh reserved Physical register 10 1Eh reserved Physical register 11 20h reserved Physical register 12 24h reserved Physic...

Page 87: ...h Physical register 17 2Eh Physical register 18 30h Physical register 19 32h Physical register 1A 34h Physical register 1B 36h Physical register 1C 38h Physical register 1D 3Ah Physical register 1E 3Ch Link register 00 3Eh Link register 01 40h Link register 02 42h Link register 03 ...

Page 88: ...cal_ID R PS Initial value 0 0 0 0 0 0 0 0 00h 0 0 Description of Each Bit BIT Bit name Action Value Function 15 8 Reserved Read 0 Always indicate 0 7 2 Physical_ID Read Indicate node No of this node determined by Self identify during processing bus reset MSB 7 LSB 2 Effective after completion of bus reset 0 Indicates that this node is not root 1 R Read 1 Indicates that this node is root 0 Indicate...

Page 89: ...ption of Each Bit BIT Bit Name Action Value Function Read Always indicate 0 15 8 reserved Write Always write 0 0 This node does not try to be root during next bus reset 7 RHB Note 1 Read Write 1 This node tries to be root during next bus reset 0 Does not perform bus reset 6 IRB Read Write 1 Performs bus reset Automatically clears to 0 at the completion of bus reset Read Indicate current gap count ...

Page 90: ...t 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 04 h R Extended Total_ports Fixed value 0 0 0 0 0 0 0 0 7 h 0 3h Description of each Bit BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 5 Extended Read Indicate that this node has the extended PHY register map MSB 7 LSB 5 Always indicate fixed value 7 h 4 reserved Read Always indicates 0 3 0 Total_ports Read Indic...

Page 91: ...t 4 Bit 3 Bit 2 Bit 1 Bit 0 06 h R Max _speed Delay Fixed value 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 5 Max_speed Read Indicate max transfer speed supporting PHY of this node MSB 7 LSB 5 Always indicates fixed value 010 b S400 4 reserved Read Always indicates 0 3 0 Delay Read Indicate Delay value at the rec...

Page 92: ...ENDER value of Self ID packet automatically transmitted by this node with the system power ON Read Indicate Jitter value at receive signal repeat MSB 5 LSB 3 Always indicates fixed value 000 b 5 3 Jitter Write Always write in 0 2 0 Pwr_class Note 3 Read Write Set pwr field POWER_CLASS value of Self ID packet automatically transmitted by this node with the system power ON Note 1 L bit value of Self...

Page 93: ...ot indicate 1 at Port_event bit during resume processing 7 Resume_Int Read Write 1 Indicates 1 at Port_event bit during resume processing 0 Does not perform short bus reset 6 ISBR Read Write 1 Performs short bus reset Automatically clears to 0 at the completion of bus reset 0 Indicates that port connection is in a loop Read 1 Indicates that port connection is in a loop 5 Loop Write Clears the bit ...

Page 94: ...nged when Int_enable bit is set at 1 Indicates that resume processing was performed when Resume_Int bit is set at 1 2 Port_event Write Clears the bit value to 0 by writing in 1 0 Disables arbitration acceleration function 1 Enab_accel Read Write 1 Enables arbitration acceleration function 0 Disables multi speed packet concatenation function 0 Enab_multi Read Write 1 Enables multi speed packet conc...

Page 95: ...Astat 2 Bstate 2 Child 2 C o nnec ted 2 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 6 Astat n Read Indicate TPA line state of 1394 port n MSB 7 LSB 6 00 invalid 01 1 10 0 11 Z 5 4 Bstat n Read Indicate TPB line state of 1394 port n MSB 5 LSB 4 00 invalid 01 1 10 0 11 Z 0 Indicates that 1394 port n i...

Page 96: ... 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R Bias 0 12 h W Disabl ed 0 R Bias 1 14h W Disabl ed 1 R Bias 2 16h W Disabl ed 2 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function Read Always indicates 0 15 2 reserved Write Always write in 0 0 Indicates that bias voltage is not detected at 1394 port n Read 1 Indicates that bias voltag...

Page 97: ... 0 0 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function Read Always indicates 0 15 8 reserved Write Always write in 0 Read Indicate max transfer speed between nodes connected to 1394 port n MSB 7 LSB 5 000 S100 001 S200 010 S400 011 111 invalid 7 5 Negotiated_ speed n Write Always write in 0 0 Does not indicate 1 at Port_event bit when Connected Bias Disabled Fault bit changed 4 ...

Page 98: ... R W Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1E h R Compliance_level Fixed value 0 0 0 0 0 0 0 0 01 h Description of Each Bit BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 0 Compliance_l evel Read Indicate that this node supports P1394a standard MSB 7 LSB 0 Always indicate fixe value 01 h ...

Page 99: ...11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 20 h R Vendor_ID hi Fixed Value 0 0 0 0 0 0 0 0 00 h 22 h R Vendor_ID mid Fixed Value 0 0 0 0 0 0 0 0 00 h 24 h R Vendor_ID lo Fixed Value 0 0 0 0 0 0 0 0 0E h Description of Each Bit BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 0 Vendor_ID Read Indicate Vendor ID of Fujitsu MSB 7 LSB 0 Always indica...

Page 100: ...Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 26 h R Product_ID hi Fixed Value 0 0 0 0 0 0 0 0 08 h 28 h R Product_ID mid Fixed Value 0 0 0 0 0 0 0 0 66 h 2A h R Product_ID lo Fixed Value 0 0 0 0 0 0 0 0 17 h Description of Each Bit BIT Bit Name Action Value Function 15 8 reserved Read Always indicate 0 7 0 Vendor_ID Read Indicate Product ID of this chip MSB 7 LSB 0 Always ind...

Page 101: ...it 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2Ch R Free_RAM 0 2E h R W Free_RAM 1 30 h R Free_RAM 2 32 h R Free_RAM 3 34 h R Free_RAM 4 36 h R Free_RAM 5 38 h R Free_RAM 6 3A h R Free_RAM 7 Initial value 0 0 0 0 0 0 0 0 00 h Description of Each Bit BIT Bit Name Action Value Function Read Always indicates 0 15 8 reserved Write Always write in 0 7 0 Free_RAM Read W...

Page 102: ...8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3Ch R W cycle master Initial Value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function Read Always indicate 0 15 6 reserved Write Always write in 0 0 Does not cycle master Read 1 Operates as cycle master if it is root 5 cycle master Write Sets the value of this bit at 1 by writing in 1 Read Always indicate 0 4...

Page 103: ...8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3E h R W cycle master Initial Value 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function Read Always indicate 0 15 6 reserved Write Always write in 0 0 Does not cycle master Read 1 Performs as cycle master if it is root 5 cycle master Write Sets the value of this bit at 0 by writing in 1 Read Always indicate 0 ...

Page 104: ...of ack_pending to all request packet Automatically transmits Acknowledge packet of ack_complete to all response packet Automatically transmits packet Code value of Acknowledge packet automatically transmitted when error is detected depends on the kind of error 3 ack mode Read Write 1 At receipt of normal packet Automatically transmits Acknowledge packet of ack_pending to Read request and Lock requ...

Page 105: ...12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 42 h R W Link init Link reset InitialValue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Description of Each Bit BIT Bit Name Action Value Function Read Always indicate 0 15 2 reserved Write Always write in 0 0 Releases initialize of LINK layer 1 Link init Read Write 1 Initializes LINK layer 0 Releases reset of LINK layer 0 Link reset ...

Page 106: ...fication MB86617A Rev 1 0 Fujitsu VLSI 101 Chapter 9 Instruction This chapter explains the instruction codes and details for respective instructions 9 1 Instruction Code Table 9 2 Description of Each Instruction ...

Page 107: ...Code Table Instruction name code Operand Start sleep 01 Remove sleep 02 Asynchronous receive 03 Remove busy mode 04 SendPHY packet 21 Asynchronous Send 31 Speed code Data FIFO init 63 FIFO select code DMA Transmit Asynchronous 71 DMA Transmit PHY packet 72 DMA Receive 73 ...

Page 108: ...chronousReceive 03 h This instruction reads the out data stored at ASYNC receive specific buffer Even though the receive data length does not satisfy with the quadlet unit this instruction stores up to quadlet unit The receive data does not have CRC code and Logical inverse part Remove busy mode 04 h This instruction releases the busy mode set due to receiving normal Asynchronous packet or Self ID...

Page 109: ...at ASYNC transmit specific buffer beforehand In case that the transmit data length does not satisfy with the quadlet unit write in 0 until quadlet unit The CRC code is to be added automatically Received Acknowledge is indicated at receive Acknowledge indicate register address 08h Note When destination ID is set at Broadcast it is completed without waiting for receipt of Acknowledge BIT Operand Nam...

Page 110: ...nous send instruction 31h DMA Transmit PHY packet 72h This instruction writes in the transmit PHY packet to ASYNC transmit specific buffer using DMA transfer Assert the DREQ signal after issuing this instruction Negate the DREQ signal after writing in 2 bites After completion of writing in issue the Send PHY packet instruction 21h DMA Receive 73h This instruction reads out the data stored in ASYNC...

Page 111: ...1 0 Fujitsu VLSI 106 Chapter 10 Interrupt This chapter explains the inturrput factors and method for interrupt mask 10 1 Interrupt factor Indicator Register interrupt mask Setting Register 10 2 Interrupt 10 3 Description of Interrupt ...

Page 112: ...ask R INT 17 INT 18 INT 19 INT 20 INT 21 INT 22 INT 23 INT 24 INT 25 INT 26 INT 27 INT 28 INT 29 INT 30 INT 31 INT 32 08h W Interrupt mask Intial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 interrupt factor Indicate Register This register indicate the interrupt content reported by this device Do not indicate the interrupt code specified MASK Do not reflect its code to XINT terminal either interrupt mask...

Page 113: ...t error INT12 Data length long error INT13 Packet format error INT14 Header CRC error INT15 Data CRC error INT16 Asynchronous receive FIFO full INT17 Asynchronous packet send INT18 Input CGMS or TSCH changed INT19 Acknowledge missing INT20 Acknowledge send INT21 Receive EMI or ODD EVEN changed INT22 First packet received INT23 Cycle start packet received INT24 Cycle start packet send INT25 Physica...

Page 114: ... node Received Bus reset INT5 Isochronous packet receive error A ch The following errors occurred at bridge Ach during packet receiving Data length value differs from that specified in the format The value of 50 60 range at CIP header is 1 at DV receiving The value of STYPE range at CIP header is other than 00000 or 00001 at DV receiving The value of DBC range at CIP header is discontinuous Header...

Page 115: ... Detected format error in packet received Occurred convention failure of packet format like Reserved range is not 0 Delete packet received INT14 Header CRC error Detected CRC error in the header of packet received Delete packet received INT15 Data CRC error Detected CRC error in the data range of packet received Do not delete packet received INT16 Asynchronous receive FIFO full ASYNC receive speci...

Page 116: ... register 01 address Phy Link reg 02h and switch to specified performance automatically INT28 Link on packet received Received Link on packet addressed to self node normally Assert LINKON terminal output simultaneously INT29 Self ID packet received Received Self ID packet normally Store data at ASYNC receive specific buffer INT30 Receive late occurred Receive late was occured Delete packet receive...

Page 117: ...chapter explains the operation of this device and displays the examples of control flow 11 1 Initialization 11 2 Self ID Packet Receiving 11 3 Asynchronous Packet Transmitting 11 4 Asynchronous Packet Receiving 11 5 Isochronous Packet Transmitting 11 6 Isochronous Packet Receiving ...

Page 118: ...st Device Figure 11 1 Example of flow for Initialization System power ON Start internal PLL Power CPS terminal to L up to 500ns Power XRESET terminal to L up to 400ns Receive BUS_RESET ReportBusresetdetected INT4 interrupt assert XINT Inner reset and release reset Start bus reset process END Read Bus reset detected INT4 interrupt No Yes ReportBus reset complete INT3 interrupt assertXINT Read Bus r...

Page 119: ...0 Fujitsu VLSI 114 11 2 Self ID Packet Receiving The example of control flow for receiving Self ID packet is shown below 11 2 1 Self ID Packet Receive during Bus Reset Process 11 2 2 Self ID Packet Receive after Ping Packet Transmitting ...

Page 120: ...et process When 1 is written to the s ID store bit of mode control register refer to 7 1 the self ID packet in the bus reset process can be received and the data removing the logical inverse section is stored in the Asynchronous receive FIFO and Asynchronous transmit FIFO 512 bytes maxixum When the number of total data exceeds 512 bytes the overflown data are discarded Bus reset force clears FIFO ...

Page 121: ...assert XINT Assert XINT Read Bus reset detected INT4 interrupt recv busy bit 0 Store received Self ID packet to Asynchronous receive buffer Report Bus reset completed INT3 assert XINT interrupt Read Bus reset completed INT3 interrupt recv busy bit 1 Set FIFO according to FIFO mode Clear Asynchronous receive buffer Note 1 1 Bus reset completed Yes No Bus reset completed No Yes Report Bus reset comp...

Page 122: ...us receiving FIFO 256 byte and Asynchronous transmitting FIFO 256 byte are cleared Asynchronous transmit FIFO and Bridge FIFO are combined to be set in Asynchronous transmit buffer Set Asynchronous receive FIFO to Asynchronous receive buffer When Asyn FIFO sel is 0 Asynchronous receive FIFO 256 byte and Asynchronous transmit FIFO 256 byte are cleared and re set Asynchronous receive FIFO to Asynchr...

Page 123: ...ion from Pin packet transmitting to Self ID packet receiving START Issue Send PHY packet 21h Issue instruction Receive TransmitPHYpacket 21h instruction Read Asynchronous transmit buffer Transmit Ping packet Arbitration result ReportPhysicalpacketsend interrupt INT25 assertXINT Store received Self ID packet in Asynchronous receive buffer Arbitration procedure END Read Physical packet send interrup...

Page 124: ...nchronous receive 03h instruction Read the data of one word from receive Asynchronous data port Read flag status register END 0 1 data req bit Read one word of received data and increment the read pointer Of receive buffer recv busy bit 0 Issue Remove busy 04h instruction Prepare for reading received data Receive Remove busy 04h instruction FIFO remote mode for receiving completed ...

Page 125: ...ronous transmit FIFO Note1 Store the data to be transmit previously in Asynchronous transmit FIFO Note2 If the transmitting length is below the digit of quadret write 0 there up to quadret unit Note3 The device can automatically attaches CRC code START Write one word the data to be transmitted in Asynchronous transmit data port Number of residual transfer byte Number of residual transfer byte minu...

Page 126: ...uction Read Asynchronous transmit buffer Transmit Asynchronous packet Arbitration result Acknowledge received Report Asynchronous packet send INT17 interrupt assert XINT Report Acknowledge missing INT20 interrupt assert XINT After the transfer of DATA_END release bus and wait Asynchronous packet receiving Arbitration procedure END Read Asynchronous packet transmit INT17 interrupt ReadAcknowledge m...

Page 127: ...LSI S pecification MB86617A Rev 1 0 Fujitsu VLSI 122 11 4 Asynchronous Packet Receiving The example of control flow for receiving Asynchronous packet is shown below ...

Page 128: ...ynchronous receive buffer Check Header CRC Transmit Acknowledge packet Report Asynchronous packet receive INT9 interrupt assert XINT NG 1 recv busy bit Transmit Ack_busy_X and discard received packet recv busy bit 1 Report Asynchronous Receive FIFO full INT16 interrupt assert XINT Read Asynchronous Receive FIFO full INT16 interrupt Read Asynchronous packet received INT9 interrupt OK Read Header CR...

Page 129: ...w quadret digid it is stored by quadret unit Note2 CRC code is not included in the data START Issue Asynchronous receive 03h instruction Read 1 word of the data from receive Asynchronous data port Read flag status register END 0 1 data req bit Read 1 word of received data and increment read pointer of receive buffer recv busybit 0 Issue Remove busy 04h instruction Prepare for reading received data...

Page 130: ...LSI S pecification MB86617A Rev 1 0 Fujitsu VLSI 125 11 5 Isochronous Packet Transmitting The example of control flow for transmitting Isochronous packet is shown below ...

Page 131: ... occurred INT32 interrupt assert XINT Read Transmit late occurred INT32 interrupt Discard source packet and transmit empty packet Transmit Late Yes No Isocycle Yes Transmit source packet to CP LSI START Store source packet in FIFO at TSPIF Input the source packet data and clock into TSPIF port Receive processed source packet from CP LSI and store it in FIFO at Bridge Arbitration result Arbitration...

Page 132: ...DBSA 09h FNA 2h 36h TXFMTA 20h TXCHA Iso channel No TXFMTA 21h TXCHA Iso channel No 38h DBSB 06h FNB 3h DBSB 09h FNB 2h 3Ah TXFMTB 20h TXCHB Iso channel No TXFMTB 21h TXCHB Iso channel No 40h Set criteria for Late packet Ach 42h Set criteria for Late packet Bch 10h Set at Ach transmitting TXSTA 1 TFA Set at Ach transmitting TXSTA 1 TFA TXFMTA 1 IDSIZEA 1 DSS130 12h Set at Bch transmitting TXSTB 1 ...

Page 133: ...cessary data to registers such as Bridg and TSPIF Receive Late evaluation Report Receive late occurred INT30 interrupt assert XINT Read Receive late occurred INT30 interrupt Discard source packet Receive Late Yes No Transmit source packet to CP LSI START Store source packet in FIFO at Bridge Receive Iso packet Receive processed source packet from CP LSI and store it in FIFO at TSPIF Output source ...

Page 134: ...1Ch TSEN 1 Set TV1A TV1B TV2A TV2B according to Ch received and port DSSEN 1 Set TV1A TV1B TV2A TV2B according to Ch received and port DVEN 1 Set TV1A TV1B TV2A TV2B according to Ch received and port 40h Set criteria for Late packet Ach 42h Set criteria for Late packet Bch 3Ch Ach received RXSTA 1h RXCHA Iso channel No Bch received RXSTB 1h RXCHB Iso channel No ...

Page 135: ...n This chapter explains the system configuration of this chip 12 1 Recommended Connection for 1934 Port for one port 12 2 Recommended Connection for Cable Power Supply 12 3 Recommended Connection for Build in PLL LoopFilter 12 4 Configuration of Feedback Circuit at Crystal Oscillator ...

Page 136: ...for one port The example of recommended connection of 1934 port terminal for one port is shown below Figure 12 1 Recommended connection for 1934 port for one port For unused 1394 port TPBIAS should be open and TPA XTPA TPB and XTPB should be be connected to GND 1 F 56 56 56 56 5 1k 250pF 5 1k ｱ1 ...

Page 137: ...I 132 12 2 Recommended Connection for Cable Power Supply The example of recommended connection of cable powersupply for 1394 cable is shown below Figure 12 2 Recommended connection for cable power supply 510KΩ 5 91KΩ 5 CPS Cable Power max 33V 2 2uF ...

Page 138: ...u VLSI 133 12 3 Recommended Connection for Build in PLL Loop Filter The example of recommended connection for build in PLL loop filter is shown below FIL RF Figure 12 3 Recommended connection for build in PLL loop filter 390Ω 5 3300pF 5 5 1KΩ 5 ...

Page 139: ...dback Circuit at Crystal Oscillator The example of configuration of feedback circuit at crystal oscillator is shownbelow No outside resistance is needed because the feedback resistance is built in Figure 12 4 Configuration of feedback circuit at crystal oscillator XO XI 20pF 20pF ...

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