9
3.10 Header for Debug Signals
CCFL Signals (JP208)
•
CCFL_OFF – CCFL supply control OFF
•
CCFL_IGNIT – CCFL supply control IGNITION
•
CCFL_FET2 – CCFL FET driver2
•
CCFL_FET1 – CCFL FET driver1
I
2
C Signals from SAA7111A (JP211)
•
I
2
C_SCL - Serial clock line
•
I
2
C_SDA - Serial data line
•
RES-out - Reset output (active low)
SAA7111A Signals (JP304)
•
RTC0 - Real time control output
•
VSC_IDENT - Video scaler field identification
•
ALPHA - Video scaler ALPHA
•
V
ref
- Vertical reference output signal
•
H
ref
- Horizontal reference output signal
•
C
ref
- Clock reference output
•
HS - Horizontal sync output signal
•
VS - Vertical sync output signal
•
GPSW - General purpose switch output
•
RES-out - Reset output (active low)
VIC Signals (JP401)
•
BUS_VCS_D7-0 - Video scaler data input
•
VSC_CLKV - Video scaler clock
LVDS connector (JP402)
Signals for LVDS connector
Display Signals (JP501)
•
DIS_PIXCLK - Display pixel clock
•
A_RED - Analog red
•
A_GREEN - Analog green
•
A_BLUE - Analog blue
•
DIS_HSYNC - Horizontal sync signal
•
DIS_VSYNC - Vertical sync signal
•
DIS_VREF - Display vertical reference signal
•
DIS_CK - Display clock
Display Digital Signals (JP502, JP503, JP504)
•
BUS_DIS_D7-0 - Digital display data
•
BUS_DIS_D15-8 - Digital display data
•
BUS_DIS_D23-16 - Digital display data
