Fujitsu ALL Series, Application Note, Page: 8 / 20

EXTERNAL INTERRUPTS
Chapter 3 External Interrupt Timing
MCU-AN -300203-E-V17 - 8 - © Fujitsu Microelectronics Europe GmbH
3 External Interrupt Timing
The following figure shows timing of events for external interrupt. Here it is considered that
external interrupt pin INTn is configured to detect falling edge.
Figure 3-1: External Interrupt Timing
Time required for CPU to finish the current instruction execution is dependent on type of
instruction being executed. If it is one of the interrupt deferring instructions / prefix codes then
it is definitely more than all other instructions. For further details please refer section 2.4.2 of
Interrupts application note MCU-AN-300210.
Time required for the context saving is dependent on various factors. Those are described in
section 2.4.1 of Interrupts application note MCU-AN-300210. The above mentioned time of 10
cycles is the minimum timing required for context saving.
External
interrupt
ISR
execution
Minimum 10
CPU cycles
for context
saving
Time required
for CPU to
finish current
instruction
execution
External
interrupt
recognized
by CPU
First
falling
edge at
external
interrupt
input
200 ns
delay for
noise
filtering
CPU
finishes
current
interrupt
execution
and starts
context
saving
CPU starts
external
interrupt
ISR
execution
INTn