New high-performance technology
PCI bus
Data access and expansion are easy to manage.
GP7000F uses a 66/33MHz PCI bus I/O that supports
high-speed throughput of up to 3.1 GB/sec.
New high-performance 64-bit
RISC processor - SPARC64 GP
The GP7000F uses SPARC64 GP, a new 64-bit RISC
processor. Developed by Fujitsu and offering superb
performance, SPARC64 GP fully conforms to the SPARC
V9 architecture.
SPARC64 GP high-speed technology
The technology in SPARC64 GP provides improvement
in the number of simultaneously executable instructions
being processed. Its out-of-order function reduces
processing interrupts by executing instructions as
resources are available, rather than in the order of the
program. This ensures the maximum utilization of
available processing resources. SPARC64 GP also attains
very high-speed memory access by use of high-capacity
processor cache (1st level: 128KB, 2nd level: 2/4/8MB).
Techniques such as 4-way set associative, write-back
functions in 1st level cache, and predicted branches, also
reduce the load, avoid delays, and improve operational
performance.
High-performance system bus
Fujitsu offers world-class system performance through
a combination of a high-performance system bus, a
system bus controller, and the high-speed SPARC64 GP
processor.
The GP7000F system bus operates at an effective rate
of 5.6GB/sec. Use of the industry's highest-speed
crossbar switch maximizes CPU performance in
multiprocessor configurations. This is because more than
one bus can access memory and execute at the same
time using this crossbar.
A high-performance system controller was also
developed to ensure efficient use of the bus when
operating with the maximum 8 processors. The system
controller uses parallel caching techniques to obtain
efficient high-speed data transfer and improved memory
access through high-speed control of the crossbar
switch.
SPARC64 GP
SYSTEM
CONTROLLER
High-performance system bus
[Model 600]
Crossbar 128bit/90MHzX4
PCI
64bit/66MHzX4
64bit/33MHzX4
Fast bus switching for
memory access
CPU
CPU
CPU
I / O
Summary of Contents for 200/200R
Page 1: ......
