Freescale Semiconductor PXR4030, Reference Manual

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Enhanced Direct Memory Access Controller (eDMA)
21-2 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21.1.1 Block Diagram
Figure 21-1 shows a simplified block diagram of each eDMA.
Figure 21-1. eDMA Block Diagram
21.1.2 Features
Each eDMA has these major features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source, destination addresses, transfer size, and support for enhanced
addressing modes
• Both 32- and 64-channel implementation performs complex data transfers with minimal
intervention from a host processor
— 32 bytes of data registers, used as temporary storage to support burst transfers
(refer to SSIZE bit)
— Connections to the crossbar switch for bus mastering the data movement
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a minor byte transfer count
Slave interface
eDMA
eDMA Done
Sys
tem b
u
s
Data path
Control
Address
Program model/
Slave write data
Slave write address
Bus write data
Slave read data
Bus address
eDMA engine
TCD0
TCD n – 1*
eDMA Peripheral Request
Bus read data
channel arbitration
path
SRAM
transfer control descriptor
( TCD )
SRAM
*n = 64 channels for eDMA_A
*n = 32 channels for eDMA_B