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Enhanced Time Processing Unit (eTPU2)
Freescale Semiconductor
29-19
PXR40 Microcontroller Reference Manual, Rev. 1
29.2.5
System Configuration Registers
29.2.5.1
ETPUMCR - eTPU Module Configuration Register
In the eTPUA/B module, this register is shared between eTPU A and eTPU B engines.. ETPUMCR gathers
configuration and status in the eTPU system, including a Global Exception. It is also used for configuring
the SCM (Shared Code Memory) operation and test.
Base + 0x000
Figure 29-3. ETPUMCR Register
GEC— Global Exception Clear
This write-only bit negates Global Exception request and clears Global Exception status bits MGE1,
MGE2, ILF1, ILF2 and SCMMISF.
0x9F4
ETPUC31SCR_B—eTPU B Channel 31 Status
and Control Register
32
R/W
0x0000_0000
0x9F8
ETPUC31HSRR_B—eTPU B Channel 31 Host
Service Request Register
32
R/W
0x0000_0000
0x9FC - 0x7FFF
Reserved
0x8000 - 0x97FF
SPRAM—Shared Parameter RAM
—
—
—
—
0xC000 - 0xFFFF SPRAM—Shared Parameter RAM - PSE mirror
2
—
—
—
—
0x10000 -
0x15FFF
3
SCM—Shared Code Memory
4
—
—
—
—
1
This register is not implemented in some MCUs; see
Section 29.2.5.4, ETPUSCMOFFDATAR - eTPU SCM Off-range
2
Parameter Sign Extension access area, see
Section 29.3.2.3, Parameter Access
.
3
When the size not the maximum, the unused SCM address range returns the value of the register ETPUSCMOFFDATAR.
4
SCM access is available only when bit VIS=1 on register ETPUMCR, under certain conditions (see
ETPUMCR - eTPU Module Configuration Register
). SCM can only be written in 32 bit accesses.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
WDTO
1
WDTO
2
MGE
1
MGE
2
ILF1
ILF2
0
0
0
SCMSIZE
W
GEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
SCMSIZE
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
SCM
MISC
SCM
MISF
SCM
MISE
N
0
0
VIS
0
0
0
0
0
GTBE
W
SCM
MISC
C
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Table 29-5. Detailed Memory Map eTPU A/B (continued)
Offset
Register
Bits
Access
Reset Value
Section/Page
Summary of Contents for PXR4030
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