Freescale Semiconductor PXR4030, Reference Manual

Page: 1078 / 1434

Enhanced Queued Analog-to-Digital Converter (EQADC)
27-96 Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
NOTE
Due to legacy reasons, the EQADC will always wait 120 ADC clocks before
issuing the first conversion command following the enabling of one of
on-chip ADCs, or the exiting of stop mode. There are two independent
counters checking for this delay: one clocked by ADC0_CLK and another
by ADC1_CLK. Conversion commands can start to be executed whenever
one of these counters completes counting 120 ADC clocks.
27.7.6.2 ADC Clock and Conversion Speed
The clock input to the ADCs is defined by setting the ADC0/1_CLK_SEL and the ADC0/1_CLK_PS
fields in the ADC0_CR and ADC1_CR. When the ADC0/1_CLK_SEL is set, the ADC clock frequency
is the same as the platform clock, but it has the inverted phase. When it is clear, the ADC0/1_CLK_PS
field selects the clock divide factor by which the platform clock will be divided as showed in
Table 27-22 .
The ADC clock frequency is calculated as below and should be lower than the maximum value specified
to the ADC analog block. This is also the maximum frequency of platform clock when the
ADC0/1_CLK_SEL is asserted.
Figure 27-62 depicts how the ADC clocks for ADC0 and ADC1 are generated.
Figure 27-62. ADC0/1 Clock Generation
ADCClockFrequency
PlatformClockFrequency MHz
 
PlatformClockDivideFactor
--------------------------------------------------------------------------------------
ADCClockFrequency 15 MHz
  
; =
Divide by:
2, 4, 6, .. , 60, 62, 64
ADC0 Control Register
ADC0_CLK_PS
To ADC0
Platform Clock Divider
Platform Clock
ADC0Clock
SEL
ADC0_CLK_SEL
Divide by:
2, 4, 6, .. , 60, 62, 64
ADC1 Control Register
ADC1_CLK_PS
To ADC1
Platform Clock Divider
Platform Clock
ADC1Clock
SEL
ADC1_CLK_SEL