PowerQUICC III Performance Monitors, Rev. 2
Freescale Semiconductor
3
Performance Metrics
3.1
Counter Events
PMC0 is a 64-bit counter specifically designed to count core complex bus (CCB) clock cycles. This
counter is started automatically out of reset and continually counts platform clock cycles. PMC1-PMC9
are 32-bit counters that can monitor up to 576 events.
Counter events are subdivided into two groups:
•
Reference (Ref:#)
- Possible to count these events on any of the nine counters PMC1-PMC9.
•
Counter-Specific (C[0-3]:#)
- Can only be counted on the specific counter noted. For example, an
event assigned to counter PMC2 is shown as C2:#
4
Performance Metrics
The use of the on-chip performance monitors to gather data is relatively straightforward. Using the data to
calculate meaningful performance metrics presents a much bigger challenge.
Table 1
presents metrics
commonly used for performance analysis and characterization. These include:
•
Instructions per cycle (IPC)
•
Instructions per packet (IPP)
•
Packets per second (PPS)
•
Branch misses per total branches (%)
•
Branches per 1000 instructions
•
L1 instruction cache miss rate
•
L1 data cache miss rate
•
L2 cache core miss rate
•
L2 cache non-core miss rate
•
Memory system page hit ratio
Note that because these calculations make use of both the core events and the system events, we
differentiate between them by a two-letter prefix:
•
CE - Core Event
•
SE - System Event
To specify an event, this prefix is followed by the event number, as defined in the core and system manuals.
For example, CE:Ref:0 refers to Core Event, Reference 0, which according to the
Power PC e500 Core
Family Reference Manual
refers to processor cycles. SE:C0
would refer to System Event, Counter 0, which
according to the device-specific reference manuals corresponds to CCB (platform) clock cycles.
Note that for counter-specific events, an offset of 64 must be used when programming the field, because
counter-specific events occupy the bottom 4 values of the 7-bit event fields.
