Freescale Semiconductor
Application Note
© 2008-2014 Freescale Semiconductor, Inc. All rights reserved.
This application note describes aspects of utilizing the core
and device-level performance monitors on PowerQUICC
III
(PQ3). Included are example calculations to aid in
interpreting data collected.
1
Performance Monitors
PowerQUICC
III processors are the first family of
PowerQUICC processors to include performance monitors
on-chip. These include both core performance monitors,
described in detail in the
Power PC
®
e500 Core Family
Reference Manual
, as well as device-level performance
monitors, described in detail in the product-specific
reference manual.
The e500 core level performance monitors enable the
counting of e500-specific events, for example, cache misses,
mispredicted branches, or the number of cycles an execution
unit stalls. These are configured by a set of special purpose
registers that can only be written through supervisor-level
accesses. The core-level event counters are also available
through a read-only set of user-level registers.
The device-level performance monitors can be used to
monitor and record selected events on a device level. These
Document Number: AN3636
Rev. 2, 03/2014
Contents
1. Performance Monitors . . . . . . . . . . . . . . . . . . . . . . . . 1
2. e500 Core Performance Monitors . . . . . . . . . . . . . . . . 2
3. Device Performance Monitors . . . . . . . . . . . . . . . . . . 2
4. Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5. Data Collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6. Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7. Data Presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PowerQUICC III Performance
Monitors
Using the Core and System Performance Monitors
