Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
11-6 Freescale Semiconductor
Internal Memory Subsystem
11.3 Data Channel and Write Queue (DCache)
The data channel and write queue is a two-way channel for reading and writing information from
the core to/from higher level memory (M2 or L2) and Control Memory (internal blocks and
external peripherals) spaces. The DCache, which operates at core speed, keeps the recently
accessed data. Whenever addressed data (from a cacheable memory area) is found in the array, it
is immediately made available to the core (DCache hit) in a read, and updated if written to. When
the required address is not found in the array, a DCache miss occurs, and the data is loaded to the
DCache from the external (not part of the DSP core subsystem) memory by the DFU, and driven
to the core. The DFU operates in parallel with the core and implements a pre-fetch algorithm to
load to the DCache, information that with high probability will be needed soon, thus reducing the
number of data cache misses. The channel differentiates between cacheable and non-cacheable
addresses. For cacheable addresses, it supports the write-back allocate writing policy. The
selection is made on an address segment basis, as programmed in the MMU. The data channel
has the following features:
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Handling 2 parallel core accesses Xa/Xb each with a width of 1, 2, 4 or 8 bytes
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Supports both cacheable and non-cacheable accesses concurrently, as identified in the
MMU based on their address ranges.
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Task-extended virtually addressed cache. The 8-bit task ID from the MMU is stored as
part of the line tag, which allows a task-specific cache image that is not overridden by
other tasks that use the same virtual address. This feature can support multi-task
mechanism. This extended tag is named ETAG in this chapter.
„
Supports cacheable shared memory between tasks, that is marked by the MMU according
to the memory range, and is stored in the cache with task ID 0.
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Serves a cache hit access without wait states (except memory conflicts).
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Upon a cache miss, issues 128-bit accesses to the higher level memory
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Upon a cache miss, could be programmed to issues pre-fetch accesses that will bring in
data until the end of the cache line (256 bytes).
— Pre-fetching is aborted in case of a new miss, on a burst size boundary.
— Programmable burst size of 1 or 4 VBRs.
„
Miss access that is identified as being pre-fetched (pre-fetch hit), will stall the core for
reduced number of wait states relative to a simple miss.
„
Cache miss upon a cacheable write performs a read first (write-allocate policy).
„
Supports write back policy for updating higher level memory through the WBB.
„
Hazard detection for reads that use data that was flushed and is still in the Write-Back
Buffer; The access is stalled until the write back is complete.
„
Supports Pseudo-LRU (PLRU) as the cache Line Replacement Mechanism (LRM).
„
Partial lock allows locking of a subset of cache lines based on ways boundaries, to reduce
cache restoration penalty of a restored task. Data can be locked in the cache, thus