Freescale Semiconductor MSC8144E, Reference Manual

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MSC8144E Reference Manual, Rev. 3
26-48 Freescale Semiconductor
Security Engine (SEC)
26.4.3.11 AESU FIFOs
AESU uses an input FIFO/output FIFO pair to hold data before and after the encryption process.
Normally, the channels control all access to these FIFOs. For core processor-controlled
operation, a write to anywhere in the AESU FIFO address space enqueues data to the AESU
input FIFO, and a read from anywhere in the AESU FIFO address space dequeues data from the
AESU output FIFO.
Writes to the input FIFO go first to a staging register which can be written by byte, 4-byte, or
8-byte accesses. When all 8 bytes of the staging register are written, the entire 8 bytes is
automatically enqueued into the FIFO. If any byte is written twice between enqueues, it causes an
error interrupt of type AE from the EU. When writing the last portion of data, it is not necessary
to write all 8 bytes. Any last bytes remaining in the staging register are automatically padded with
zeros and forced into the input FIFO when the AESU End_of_message register is written.
The output FIFO is readable by byte, 4-byte, or 8-byte accesses. When all 8 bytes of the header
are read, that 8 bytes is automatically dequeued from the FIFO so that the next 8 bytes (if any)
becomes available for reading. If any byte is read twice between dequeues, it causes an error
interrupt of type AE from the EU.
Overflows and underflows caused by reading or writing the AESU FIFOs are reflected in the
AESU Interrupt Status Register.
The AESU fetches data 128 bits at a time from the input FIFO. During processing, the input data
is encrypted or decrypted with the key and initialization vector (CBC mode only) and the results
are placed in the output FIFO. The output size is the same as the input size.
The input FIFO may be written any time the number of 8-byte sets currently in the input FIFO (as
indicated by the IFL field of the AESU Status Register) is less than 32. There is no limit on the
total number of bytes in a message. The number of bits in the final message block must be set in
the Data Size Register.
The output FIFO may be read any time the OFR signal is asserted (as indicated in the AESU
Status Register). This will indicate that the number of bytes in the output FIFO is at or above the
threshold specified in the Mode Register.
For AES-CCM mode, the input data stream to the input FIFO consists of the CCM Header,
followed by the Additional Authenticated Data (AAD), followed by Plaintext if encrypting, or
Ciphertext if decrypting. Note that AESU only supports 2 byte CCM headers and does not
support extended CCM headers.
26.4.4 Message Digest Execution Unit (MDEU)
In typical operation, the MDEU is used through channel-controlled access, which means that
most reads and writes of MDEU registers are directed by the SEC channels. Driver software