6-16
MPC860T (Rev. D) Fast Ethernet Controller Supplement
MOTOROLA
PRELIMINARYÑSUBJECT TO CHANGE WITHOUT NOTICE
6.2.16 FIFO Receive Start Register (R_FSTART)
The R_FSTART register, shown in Figure 6-16, is programmed by the user to indicate the
starting address of the receive FIFO. R_FSTART marks the boundary between the transmit
and receive FIFOs. The transmit FIFO uses addresses from X_FSTART to R_FSTART - 4.
The receive FIFO uses addresses from R_FSTART to R_BOUND, inclusive.
Hardware initializes R_FSTART with a value that is microcode-dependent after
ECNTRL[ETHER_EN] is set. R_FSTART only needs to be written to change the default
value.
Table 6-18 describes R
Ñ
FSTART Þelds.
6.2.17 Transmit Watermark Register (X_WMRK
The X_WMRK register is used to control the amount of data required in the transmit FIFO
before transmission of a frame can begin. This allows the user to minimize transmit latency
(X_WMRK = 0x) or allow larger bus access latency (X_WMRK = 11) due to contention
22Ð29
R_BOUND
Read-only. Highest valid FIFO RAM address.
30Ð31
Ñ
Reserved. Should be written to zero by the host processor.
Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Field
Ñ
Reset
0000_0000_0000_0000
R/W
Read/write
Addr
0xED0
Bits
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Field
Ñ
1
R_FSTART
Ñ
Reset
0000_0000_0000_0000
R/W
Read/write
Addr
0xEDC
Figure 6-16. R_FSTART Register
Table 6-18. R_FSTART Field Descriptions
Bits
Name
Description
0Ð21
Ñ
Reserved. Note all bits read back as 0 except for 21 which returns a 1.
22Ð29
R_FSTART Address of Þrst receive FIFO location. Acts as a delimiter between receive and transmit FIFOs.
30Ð31
Ñ
Reserved. Should be written to zero by the host processor.
Table 6-17. R_BOUND Field Descriptions
Bits
Name
Description
F
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e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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