Freescale Semiconductor MPC8569E-MDS-PB Hardware Getting Started Manual Download Page 14 | Manualshive

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MPC8569E-MDS-PB Hardware Getting Started, Rev. 3.1

14

Freescale Semiconductor

Switch Default Settings

SW10 Configuration: AUX

SW10.1-SW10.3: Host/Agent Configuration

SW10.4: Platform Speed

• ‘0’: CCB frequency is < 333 MHz.
• ‘1’: (Default) CCB frequency is > or = to 333 MHz.

SW10.5: Core speed

• ‘1’: Core clock frequency is < or = to 1000 MHz.
• ‘0’: (Default) Core clock frequency is > 1000 MHz.

SW10.6: eLBC ECC Enable

• ‘0’: (Default) eLBC ECC is disabled after POR.
• ‘1’: eLBC ECC is enabled after POR.

SW10.7: Fuse PLL Override Disable

• ‘0’: PLL parameters are controlled by fuse bits.
• ‘1’: (Default) PLL parameters are controlled by plugs.

SW10.8: Fuse Read Enable

• ‘0’: Fuse reads are disabled during the reset sequence.
• ‘1’: (Default) Fuse reads are enabled during reset sequence.

8

7

6

5

4

3

2

1

READ FUSE

PLL FUSE

ELBC ECC

CORE SPEED

PLAT SPEED

HOST_AGT2

HOST_AGT1

ON ’0’

HOST_AGT0

Value (Binary)

Description

000

MPC8569E acts as an Agent for PCI Express (EP)
and both SRIO interfaces.

001

MPC8569E acts as an Agent for both SRIO interfaces.

010

Reserved

011

Reserved

100

Reserved

101

Reserved

110

MPC8569E acts as a PCI Express EP.

111

(Default) MPC8569E acts as the Host-processor/RC.

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Summary of Contents for MPC8569E-MDS-PB

Page 1: ...nt IDE such as Freescale s CodeWarrior but instructions for working with the IDE are beyond the scope of this document NOTE The terms PEX and PCIe are interchangeable However as the modules are stamped PEX the document uses this term Contents 1 Revisions Table 2 2 Definitions Acronyms and Abbreviations 2 3 Related Reading 5 4 Hardware Kit Contents 6 5 Schematic CS and PS Views 7 6 Switch Default S...

Page 2: ...ukht Hadas Khen Revised content 22 June 2009 3 1 Vladimir Yukht Hadas Khen BCSR changes Table 2 Definitions Acronyms and Abbreviations Usage Description ADDR Address ADS Application Development System BCSR Board Control and Status Register BVDD Local Bus Volt Direct Current CCB Platform Clock CKE DDR Clock Enable CLKIN Clock Input interchangeable with SYSCLK CLKOUT Clock Output CNTR ISP Control PL...

Page 3: ...ent Environment IO Input Output IRSENSE Service Voltage Drop Testing JTAG Joint Test Access Group IEEE Std 1149 1 LED Light emitting Diode LYNX Internal terminology interchangeable with SerDes LVDD QUICC Engine Block UCC1 UCC4 Voltage MCK E DDR Master Clock MDIC DDR Memory Driver Impedance Calibration MEMC Memory Controller MMC Multi Media Card MPI Metallized Particle Interconnect Matrix NAND FLAS...

Page 4: ...n Register RGMII Reduced General Media Independent Interface RMII Reduced Media Independent Interface ROM Read Only Memory RTC Real Time Clock SD Secure Digital Card SDHC Secure Digital High Capacity Card SerDes Serializer Deserializer High Speed Serial Communication Lines e g PEX PCIe SRIO SGMII etc SGMII Serial Gigabit Media Independent Interface SHMOO Graphical representation of selected test p...

Page 5: ...eceiver Transmitter UCC Universal Communication Controller UEM Universal Ethernet Module UPC Universal Programmable Controller USB Universal Serial Bus V Volt VDD Common Power Supply Terminals Document Description CodeWarrior Kit Configuration Guide Complete HW setup explanation Kit Configuration Guide explains how to set up and use each SW component in the development kit MPC8569E PowerQUICC III ...

Page 6: ... SRIO_LOOPBACK CARD 2 6 Bootwiz 1 Cables 7 RS 232 standard serial cable with two 9 pin connectors 2 8 FSL adaptor cable with one 10 pin and two RS 232 connectors 1 9 ETH cables 4 with RJ45 connectors 10 ETH loop back cables 4 Power Supply and USB TAP 11 AC DC 5V 8A power supply 12 CodeWarrior USB TAP Miscellaneous 13 Allen key 14 UEM plastic guide pins 6 15 Auxiliary UTAP to CNTR ISP connector 1 P...

Page 7: ...MP6 MP5 C497 C496 C355 C261 C323 C268 C233 C379 C270 C367 C192 C264 C232 C239 C238 C420 C244 C245 C201 C199 C205 C203 C259 C248 C250 C191 C487 C206 C207 C421 C583 C584 C580 C581 C578 C577 C573 C572 C567 C326 C427 C500 C498 C329 C372 C371 C494 C488 C493 C489 C208 C480 C217 C177 C178 C530 C277 C481 C252 C213 C518 C416 C415 C175 C417 C558 C224 C369 C325 C479 C556 C553 C314 C181 C254 C215 C227 C365 C5...

Page 8: ...k modes see Table 4 NOTE Ensure DIP switches are set according to default values Figure 4 MPC8569E MDS PB DIP Switch Locations Table 4 MPC8569E MDS PB Default Configurations Mode Value BVDD Voltage 3 3V only CCB Clock 533MHz SYSCLK CLKIN 66 67 MHz Core Clock 1067MHz MHz DDR CLK 400 MHz DDR3 LVDD1 and LVDD2 Voltage 2 5V PTP CLK 66 67 MHz QE Clock 533MHz RTC CLK 66 67 MHz SerDes REF CLK 100 MHz SRIO...

Page 9: ...R2 1 8V CKE low at reset SW5 6 DRAM Mode 0 Primary and secondary DDR is enabled 32 bit width data bus 1 Default Primary DDR is enabled 64 bit width data bus secondary DDR is disabled SW5 7 DDR Speed 1 Default DDR clock frequency 500MHz 0 DDR clock frequency or to 500MHz SW5 8 Disables DDR2 Phase Reset Logic 0 DDR controller disables MCKE at reset a few cycles later MCK is disabled 1 Default At res...

Page 10: ...arity isn t inverted SW6 7 QE UCC1 and UCC3 Voltage Select 0 QUICC Engine UCC1 3 GB Ethernet interface operates at 3 3V 1 Default QUICC Engine UCC1 3 GB Ethernet interface operates at 2 5V SW6 8 QE UCC2 and UCC4 Voltage Select 0 QUICC Engine UCC2 4 GB Ethernet interface operates at 3 3V 1 Default QUICC Engine UCC2 4 GB Ethernet interface operates at 2 5V 8 7 6 5 4 3 2 1 LVDD_SEL1 LVDD_SEL0 SDHC QE...

Page 11: ...ck Configuration 0 SerDes expects a 125 MHz reference clock frequency 1 Default SerDes expects a 100 MHz reference clock frequency 8 7 6 5 4 3 2 1 SRDS REFCLK CORE_PLL2 CORE_PLL1 CORE_PLL0 SYS_PLL3 SYS_PLL2 SYS_PLL1 ON 0 SYS_PLL0 Value Binary CCB Clock SYSCLK Ratio 0000 Reserved 0001 Reserved 0010 2 1 0011 3 1 0100 4 1 0101 5 1 0110 6 1 0111 7 1 1000 Default 8 1 1001 Reserved 1010 Reserved 1011 Re...

Page 12: ...z 0001 SRIO1 1x 2 5 Gbps Lane A SRIO2 1x 2 5 Gbps Lane B SGMII x2 1 25 Gbps half speed Lanes E F 100 MHz 0010 SRIO1 1x 2 5 Gbps half speed Lane A SRIO2 1x 2 5 Gbps half speed Lane B SGMII x2 1 25 Gbps half speed Lanes E F 100 MHz 0011 SRIO1 1x 3 125 Gbps Lane A SRIO2 1x 3 125 Gbps Lane B 125 MHz 0100 PCI Express x1 2 5 Gbps Lane A SGMII x2 1 25 Gbps half speed Lanes E F 100 MHz 0101 PCI Express x2...

Page 13: ... Boot sequencer is enabled Loads configuration information from an I2C1 interface ROM a valid ROM must be present 11 Default I2 C ROMs not accessed Boot sequencer is disabled SW9 8 Reset Configuration Source 0 RCW is read through I2C 1 Default RCW is read through IO pin sampling 8 7 6 5 4 3 2 1 SOURCE SEQ1 SEQ0 CPU_CFG ROM_LOC3 ROM_LOC2 ROM_LOC1 ON 0 ROM_LOC0 Value Binary Description 0000 PCI Expr...

Page 14: ...W10 7 Fuse PLL Override Disable 0 PLL parameters are controlled by fuse bits 1 Default PLL parameters are controlled by plugs SW10 8 Fuse Read Enable 0 Fuse reads are disabled during the reset sequence 1 Default Fuse reads are enabled during reset sequence 8 7 6 5 4 3 2 1 READ FUSE PLL FUSE ELBC ECC CORE SPEED PLAT SPEED HOST_AGT2 HOST_AGT1 ON 0 HOST_AGT0 Value Binary Description 000 MPC8569E acts...

Page 15: ...erDes a Default OPEN J11 Socket System Clock Oscillator 66 67 MHz Default Inserted J12 Socket PTP Clock Oscillator 66 67 MHz Default Inserted J13 16 pin Header COP Interconnection External USB TAP interconnection J14 Header GETH1 Default OPEN J15 Header GETH3 Default OPEN J16 Header SerDes e Default OPEN J17 Header SerDes b Default OPEN J18 Header System Clock Source Selection 1 2 External SYSCLK ...

Page 16: ...S cntr PLD programming P2 Connector 5V IN power jack MPC8569E MDS PB 5V power jack P3 Socket SD Card Slot located on PS Used for SD MMC card insertion 1 An auxiliary connector UTAP to CNTR ISP is used to reprogram the U86 onboard PLD Altera Insert auxiliary connector into U29 header then attach USB TAP connector to auxiliary connector Table 5 MPC8569E MDS PB Connector Default Settings Type Descrip...

Page 17: ... Position Description Default SW2 POWER ON OFF Press SW2 to Power ON OFF all PB components Powered from an external 5V power supply via the P2 power jack Combined mode 5V on PIB power supply via riser connectors SW3 HRESET Press SW3 for HRESET of the PB SW4 SRESET Press SW4 for SRESET of the PB Retains clock and chip select data contents despite the reset Figure 6 MPC8569E MDS PB Push Button Locat...

Page 18: ... 8V voltage supply Board is OFF no power or DDR3 voltage supply D4 ASLEEP Orange MPC8569 HRESET is asserted MPC8569 HRESET isn t asserted D5 USB POWER Green BCSR17 2 is low USB power applied to J1 USB connector BCSR17 2 is high USB power isn t applied to USB connector D6 5VIN Yellow 5V input power applied to board No power supplied to the board D7 REG CFG Orange MPC8569 configurable from BCSR MPC8...

Page 19: ...DDR2 100 DDR3 110 R W 3 CFG_DDR_FB_SEL DDR QE and Platform PLL Feedback Select 0 gclk matched long DDR QE and Platform PLLs feedback path 1 Default local short DDR PLL feedback path SW5 4 sampled at HRESET 1 R W 4 CFG_DDR_TYPE DDR Dram Type DDR2 or DDR3 0 DDR3 of 1 5V and low CKE at reset 1 Default DDR2 of 1 8V and low CKE at reset SW5 5 sampled at HRESET DDR3 0 DDR2 1 R W 5 CFG_DDR_MODE DDR Dram ...

Page 20: ... W Bit Config Signals Function Default Att 0 3 CFG_PORT_SEL 0 3 IO Select Configuration for SerDes SW8 1 4 sampled at HRESET 0111 R W 4 6 CFG_RIO_ID 5 7 RapidIO Device ID 5 7 SW8 5 7 sampled at HRESET 000 R W 7 CFG_RIO_SYS_SIZE RapidIO System Size 0 Large system size with a maximum of 65 536 devices 1 Small system size with a maximum of 256 devices SW8 8 sampled at HRESET 1 R W Bit Config Signals ...

Page 21: ...tion input configures internal logic for proper operation with core clock frequencies 0 Core clock frequency or to 1000MHz 1 Core clock frequency 1000MHz SW10 5 sampled at HRESET 1 R W 5 CFG_ELBC_ECC POR configuration input enables eLBC ECC checking on booted external local bus interface 0 eLBC ECC disabled after POR 1 eLBC ECC enabled after POR SW10 5 sampled at HRESET 0 R W 6 CFG_FUSE_OVR_DIS 0 ...

Page 22: ...2G UPC1_EN 0 BCSR6 7 disable If bit 1 TDM2G is enabled RMII7 BCSR6 7 should be 0 1 R W 7 RMII7 UPC1_EN 0 BCSR6 7 disable If bit 1 RMII7 is enabled TDM2G BCSR6 6 should be 0 1 R W Bit Config Signals Function Default Att 0 UCC1_GETH 1 Enable UCC1_GETH RGMII or RTBI 0 Disable UCC1_GETH OR enable UCC1_RMII RMII1 on PIB 1 R W 1 UCC1_RGMII 1 Enable RGMII 0 Disable RTBI AND enable RMII on PIB 1 R W 2 UCC...

Page 23: ...C 1 Enable 0 Disable 0 R W 5 CS_NOR 1 Boot from NAND_FLASH 0 Boot from NOR_FLASH 0 R W 6 UEM Marvell PHY RESET 1 RESET UEM3 UCC3 and UEM4 UCC4 0 Normal operation 0 R W 7 DDRDRV_SEL 1 MEMC1 2 MDIC0 1 36 5OHm 0 MEMC1 2 MDIC0 1 18OHm 1 R W Bit Config Signals Function Default Att 0 UCC3_GETH 1 Enable UCC3_GETH Use UEM module on PB for RGMII or RTBI 0 Disable UCC3_GETH OR enable depending upon UCC3_RMI...

Page 24: ...or RTBI 0 Disable UCC4_GETH OR enable UCC4_RMII RMII4 on PIB or TDM1C 1 R W 1 UCC4_RGMII 1 Enable RGMII on UEM 0 Disable RTBI on UEM AND enable RMII3 on PIB 1 R W 2 UCC4_RTBI 1 Enable RTBI on UEM 0 Disable RGMII on UEM AND enable RMII3 on PIB 0 R W 3 RMII4__nSMII4 1 Enable RMII on PB UEM 0 Enable SMII on PB UEM UCC8 SMII unsupported 1 R W 4 R_SMII4_nRMII4 0 Enable RMII on PB UEM 1 Enable SMII on P...

Page 25: ...4 R_SLEW0 Select slew rate for GETH input clock 0 R W 5 R_SLEW 1 R W 6 SSC0 Select SerDes clock synthesizer spread spectrum mode 1 R W 7 SSC1 1 R W Bit Config Signals Function Default Att 0 PCIE_CLKDIS 1 Enable PEX clock 0 Disable PEX clock 1 R W 1 TRIGIN For internal use only 0 Z R W 2 RMII6 1 Enable RMII6 on PIB and TDM2F 1 0 Disable RMII6 AND enable ATM or POS 1 R W 3 RMII8 1 Enable RMII8 on PI...

Page 26: ...RMII PHY TDM framer and or ATM PHY 0 R W 7 ISOLATE_GPIO 1 For RMII6 and RMII7 operation 0 For UPC1 operation 0 R W 1 I2C PCA9555 address 26H should drive output register 1 0 to 1 Bit Config Signals Function Default Att 0 7 R_PS 0 7 Internal Use Only 1 1 R W Bit Config Signals Function Default Att 0 4 R_PS 8 12 Internal Use Only 11111 R W 5 TDM1G_EN 1 TDM1G_EN enabled 0 TDM1G_EN disabled 0 R W 6 PR...

Page 27: ...8 DIS 1 Enable UCC8 RMII on PIB and TDM1H AND disable SMII8 0 Enable SMII8 SMII unsupported 1 R W 6 TDM1F 1 Enable TDM1F 0 Disable TDM1F 1 R W 7 RUART1_nQEUART 1 Enable QE_UART 0 Enable UART1 TDM1D and TDM2B 0 R W Bit Config Signals Function Default Att 0 PORESET PWR_ON Reset HRESET 0 Active 1 R W 1 TSEC0MST Reserved 1 R W 2 TSEC1MST Reserved 1 R W 3 TSEC2MST Reserved 1 R W 4 TSEC3MST Reserved 1 R...

Page 28: ...cts as Device USB powered from an external host Enables RMII6 and TDM1G 1 USB acts as Host USB supplies power to external device 0 R W 3 RUSB_MODE USB Mode 1 Host 0 Device 0 R W 4 RPRESENCE_F UEM inserted into J7 1 Present 0 Not present x R 5 RPRESENCE_E UEM inserted into J16 1 Present 0 Not present x R 6 RFLASH_RDY 1 Ready 0 Busy x R 7 FLASH_nWP 0 FLASH Write Protect 1 FLASH normal operation 0 R ...

Page 29: ...FFF MEMC1 Integrated Mode 1GB 64 20000000 3FFFFFFF MEMC2 512MB 32 40000000 7FFFFFFF Reserved 1GB 80000000 9FFFFFFF SRIO1 Outbound Window 512 MB x4 lane A0000000 BFFFFFFF SRIO2 Outbound Window 512 MB x4 lane C0000000 DFFFFFFF PEX Outbound Window 512 MB x4 lane E0000000 E00FFFFF MPC8569 Internal Map Internal Memory Register Space 1 MB 32 E0100000 E03FFFFF Reserved For future MPC8569 derivatives 3 MB...

Page 30: ...SRIOx1 SerDes Lane a b PEXx2 1xDDR3 SODIMMx64 or 2xDDR3x32 SODIMM PB powered via P2 by an external 5V power supply included in kit Option PEX EP powered via P2 of PEXx2 by an external 12V power supply PIB combined Mode MPC9569 MDS PB on PIB Includes the noted modules GETH3 4 UEM SerDes Lane e f SRIOx1 or UEM SGMII mode SerDes Lane a b SRIOx1 SerDes Lane a b PEXx2 1xDDR3 SODIMMx64 or 2xDDR3x32 SODI...

Page 31: ...re 4 Establish working environment Section 12 Procedure 5 Insert plastic guide pins into PB 1 Insert three guide pins Pins hold UEM modules used in RGMII and RTBI modes 2 Insert three guide pins Pins hold UEM modules SGMII mode used for SerDes Options 1 2 and 3 See Section 12 Set up 1 Procedure 6 Assemble and connect 5V power supply NOTE Ensure Power OFF 1 Assemble AC DC power supply kit a Cable w...

Page 32: ...CodeWarrior IDE software to work with the PB 1 Align Bootwiz module with its CS facing the board s printed COP text The PS must face switches SW5 SW10 2 Connect the Bootwiz module to the J13 COP board connector 3 Attach the USB TAP cable to the Bootwiz module s J2 connector 4 Press button SW2 to Power ON all PB components 5 Check for completion of the reset sequence Procedure 9 Attach cables per u...

Page 33: ... PEX expansion module power jack a b e f Option 1 Option 2 3 Option 4 5 SGMIIx1 SGMIIx1 SGMIIx1 SGMIIx1 PEX x2 12 V PEX x2 12 V SRIO x1 A 1 H 1 A 1 0 H 1 0 SRIO x1 A 1 H 1 A 1 0 H 1 0 SRIO x1 A 1 H 1 A 1 0 H 1 0 SRIO x1 A 1 H 1 A 1 0 H 1 0 2 5Gbaud x2PEX 5 2 5Gbaud x1PEX 4 PEXat2 5Gbaud x2PEX SGMII SGMII 3 PEXat2 5Gbaud x1PEX SGMII SGMII 2 SRIOat 2 5Gbaud x1SRIO1 SGMII SGMII 1 Frequency Informatio...

Page 34: ...ews b Insert SRIO loopback into assembled SRIOx1 modules SerDes Option 2 two UEM one PEXx1 x1 mode a Insert UEM modules into J16 and J7 b Connect ETH RJ45 cables to UEM modules c Insert PEXx2 into J10 and J17 d PEX slot now available as RC port x1 SerDes Option 3 two UEM one PEXx2 x2 mode a Repeat first three steps of Option 2 b PEX slot now available as RC port x2 See SerDes Option 2 photos UEM S...

Page 35: ... a Insert SRIOx1 modules into J16 and J7 b Insert SRIO loopback into SRIOx1 modules c Insert PEXx2 into J10 and J17 d PEX slot now available as RC port x1 SerDes Option 5 two SRIOx1 one PEXx2 x2 mode a Repeat first three steps of Option 4 b PEX slot now available as RC port x2 See SerDes Option 4 photos SRIOx1 Loopback PEX Loopback SRIOx1 PEX ...

Page 36: ...MPC8569E MDS PB Hardware Getting Started Rev 3 1 36 Freescale Semiconductor SerDes Module Set ups ...

Page 37: ...ny product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each custome...

Page 38: ...MPC8569E MDS PB Hardware Getting Started Rev 3 1 38 Freescale Semiconductor SerDes Module Set ups ...

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