Freescale Semiconductor MPC8349E PowerQUICC II Pro Hardware Specifications Download Page 20

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MPC8349E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

DUART

This section describes the DC and AC electrical specifications for the DUART interface of the
MPC8349E.

7.1

DUART DC Electrical Characteristics

Table 17

provides the DC electrical characteristics for the DUART interface of the MPC8349E.

7.2

DUART AC Electrical Specifications

Table 18

provides the AC timing parameters for the DUART interface of the MPC8349E.

Table 17. DUART DC Electrical Characteristics

Parameter

Symbol

Min

Max

Unit

High-level input voltage

+ 0.3

Low-level input voltage

–0.3

0.8

Input current (0.8 V

≤

2 V)

—

±5

High-level output voltage, I

= –100

– 0.2

—

Low-level output voltage, I

= 100

—

0.2

Table 18. DUART AC Timing Specifications

Parameter

Value

Unit

Notes

Minimum baud rate

256

baud

Maximum baud rate

>1,000,000

baud

Oversample rate

—

Notes:
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8

sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are

sampled each 16

sample.

Summary of Contents for MPC8349E PowerQUICC II Pro

Page 1: ...ment is accurate for revision 1 1 silicon and earlier For information on revision 3 0 silicon and later versions for orderable part numbers ending in A or B see the MPC8349EA PowerQUICC II Pro Integra...

Page 2: ...implement Power Architecture technology Double data rate DDR SDRAM memory controller Programmable timing for DDR 1 SDRAM 32 or 64 bit data interface up to 333 MHz data rate Four banks of memory each...

Page 3: ...Internal 2 Kbyte transmit and 2 Kbyte receive FIFOs per TSEC module MII management interface for control and status Programmable CRC generation and checking Dual PCI interfaces Designed to comply with...

Page 4: ...6 bits ECB CBC CCM and counter CTR modes ARC four execution unit AFEU Stream cipher compatible with the RC4 algorithm 40 to 128 bit programmable key Message digest execution unit MDEU SHA with 160 or...

Page 5: ...ree protocol engines on a per chip select basis General purpose chip select machine GPCM Three user programmable machines UPMs Dedicated single data rate SDRAM controller Parity support Default boot R...

Page 6: ...ng and direct mode Interrupt on completed segment and chain DUART Two 4 wire interfaces RxD TxD RTS CTS Programming model compatible with the original 16450 UART and the PC16550D Serial peripheral int...

Page 7: ...to GVDD 0 3 V 2 5 DDR DRAM reference MVREF 0 3 to GVDD 0 3 V 2 5 Three speed Ethernet signals LVIN 0 3 to LVDD 0 3 V 4 5 Local bus DUART CLKIN system control and power management I2C and JTAG signals...

Page 8: ...rating Conditions Characteristic Symbol Recommended Value Unit Notes Core supply voltage VDD 1 2 V 60 mV V 1 PLL supply voltage AVDD 1 2 V 60 mV V 1 DDR DRAM I O supply voltage GVDD 2 5 V 125 mV V Thr...

Page 9: ...e power supplies are stable there may be a period of time that I O pins are actively driven After the power is stable as long as PORESET is asserted most I O pins are three stated To minimize the time...

Page 10: ...t TJ 65 Typical2 3 2 Typical power is based on a voltage of VDD 1 2 V a junction temperature of TJ 105 C and a Dhrystone benchmark application 3 Thermal solutions may need to design to a value higher...

Page 11: ...Hz 64 bits 0 55 W 266 MHz 32 bits 0 5 W 266 MHz 64 bits 0 66 W 300 MHz 32 bits 0 54 W 300 MHz 64 bits 0 7 W 333 MHz 32 bits 0 58 W 333 MHz 64 bits 0 76 W 400 MHz 32 bits 400 MHz 64 bits PCI I O load 3...

Page 12: ...rrent 0 V VIN OVDD IIN 10 A PCI_SYNC_IN input current 0 V VIN 0 5 V or OVDD 0 5 V VIN OVDD IIN 10 A PCI_SYNC_IN input current 0 5 V VIN OVDD 0 5 V IIN 50 A Table 7 CLKIN AC Timing Specifications Param...

Page 13: ...0 4 V Notes 1 This table applies for pins PORESET HRESET SRESET and QUIESCE 2 HRESET and SRESET are open drain pins thus VOH is not relevant for those pins Table 9 RESET Initialization Timing Specifi...

Page 14: ...CFG_CLKIN_DIV See the MPC8349E PowerQUICC II Pro Integrated Host Processor Family Reference Manual 2 tCLKIN is the clock period of the input clock applied to CLKIN It is valid only in PCI host mode Se...

Page 15: ...MVREF 0 49 GVDD 0 51 GVDD V 2 I O termination voltage VTT MVREF 0 04 MVREF 0 04 V 3 Input high voltage VIH MVREF 0 18 GVDD 0 3 V Input low voltage VIL 0 3 MVREF 0 18 V Output leakage current IOZ 10 1...

Page 16: ...AC input low voltage VIL MVREF 0 31 V AC input high voltage VIH MVREF 0 31 GVDD 0 3 V MDQS MDQ MECC input skew per byte 333 MHz 266 MHz tDISKEW 750 1125 ps 1 Note 1 Maximum possible skew between a da...

Page 17: ...the clock control register For the skew measurements referenced for tAOSKEW it is assumed that the clock adjustment is set to align the address command valid with the rising edge of MCK 4 ADDR CMD in...

Page 18: ...tAOSKEW Measurement Figure 5 provides the AC test load for the DDR bus Figure 5 DDR AC Test Load Table 15 shows the DDR SDRAM measurement conditions Table 15 DDR SDRAM Measurement Conditions Symbol DD...

Page 19: ...delay numbers will strongly depend on the topology used These delay numbers show the total delay for the address and command to arrive at the DRAM devices The actual delay could be different than the...

Page 20: ...able 17 DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High level input voltage VIH 2 OVDD 0 3 V Low level input voltage VIL 0 3 0 8 V Input current 0 8 V VIN 2 V IIN 5 A High level...

Page 21: ...in Section 8 3 Ethernet Management Interface Electrical Characteristics 8 1 1 TSEC DC Electrical Characteristics All GMII MII TBI RGMII and RTBI drivers and receivers comply with the DC parametric att...

Page 22: ...Unit GTX_CLK clock period tGTX 8 0 ns GTX_CLK duty cycle tGTXH tGTX 43 75 56 25 GTX_CLK to GMII data TXD 7 0 TX_ER TX_EN delay tGTKHDX 0 5 5 0 ns GTX_CLK clock rise time VIL min to VIH max tGTXR 1 0...

Page 23: ...tGRXF 1 0 ns Note 1 The symbols for timing specifications follow the pattern of t first two letters of functional block signal state reference state for inputs and t first two letters of functional b...

Page 24: ...XH tMTX 35 65 TX_CLK to MII data TXD 3 0 TX_ER TX_EN delay tMTKHDX 1 5 15 ns TX_CLK data clock rise VIL min to VIH max tMTXR 1 0 4 0 ns TX_CLK data clock fall VIH max to VIL min tMTXF 1 0 4 0 ns Note...

Page 25: ...4 0 ns RX_CLK clock fall time VIH max to VIL min tMRXF 1 0 4 0 ns Note 1 The symbols for timing specifications follow the pattern of t first two letters of functional block signal state reference stat...

Page 26: ...LK125 reference clock duty cycle tG125H tG125 45 55 ns Notes 1 The symbols for timing specifications follow the pattern of t first two letters of functional block signal state reference state for inpu...

Page 27: ...irst two letters of functional block signal state reference state for inputs and t first two letters of functional block reference state signal state for outputs For example tTRDVKH symbolizes TBI rec...

Page 28: ...125H tG125 47 53 Notes 1 In general the clock reference symbol for this section is based on the symbols RGT to represent RGMII and RTBI timing For example the subscript of tRGT represents the TBI T re...

Page 29: ...hows the RBMII and RTBI AC timing and multiplexing diagrams Figure 14 RGMII and RTBI AC Timing and Multiplexing Diagrams GTX_CLK tRGT tRGTH tSKRGT TX_CTL TXD 8 5 TXD 7 4 TXD 9 TXERR TXD 4 TXEN TXD 3 0...

Page 30: ...cal Characteristics Powered at 2 5 V Parameter Symbol Conditions Min Max Unit Supply voltage 2 5 V LVDD 2 37 2 63 V Output high voltage VOH IOH 1 0 mA LVDD Min 2 00 LVDD 0 3 V Output low voltage VOL I...

Page 31: ...s of functional block signal state reference state for inputs and t first two letters of functional block reference state signal state for outputs For example tMDKHDX symbolizes management data timing...

Page 32: ...ld to USB clock all inputs tUSIXKH 1 ns 2 5 USB clock to output valid all outputs tUSKHOV 7 ns 2 5 Output hold from USB clock all outputs tUSKHOX 2 ns 2 5 Notes 1 The symbols for timing specifications...

Page 33: ...10 Freescale Semiconductor 33 USB Figure 16 and Figure 17 provide the AC test load and signals for the USB respectively Figure 16 USB AC Test Load Figure 17 USB Signals Output Z0 50 OVDD 2 RL 50 Outpu...

Page 34: ...evel output voltage IOL 100 A VOL 0 2 V Table 34 Local Bus General Timing Parameters DLL On Parameter Symbol1 Min Max Unit Notes Local bus cycle time tLBK 7 5 ns 2 Input setup to local bus clock excep...

Page 35: ...timings are measured at the pin 5 tLBOTOT1 should be used when RCWH LALE is not set and when the load on the LALE output pin is at least 10 pF less than the load on the LAD output pins 6 tLBOTOT2 sho...

Page 36: ...of LCLK0 for all outputs and for LGTA and LUPWAIT inputs or the rising edge of LCLK0 for all other inputs 3 All signals are measured from OVDD 2 of the rising falling edge of LCLK0 to 0 4 OVDD of the...

Page 37: ...als LA 27 31 LBCTL LBCKE LOE LSDA10 LSDWE LSDRAS LSDCAS LSDDQM 0 3 tLBKHOV tLBKHOV tLBKHOV LSYNC_IN Input Signals LAD 0 31 LDP 0 3 Output Data Signals LAD 0 31 LDP 0 3 Output Address Signal LAD 0 31 L...

Page 38: ...PM Mode Input Signal LUPWAIT tLBIXKH2 tLBIVKH2 tLBIVKH1 tLBIXKH1 tLBKHOZ1 T1 T3 Input Signals LAD 0 31 LDP 0 3 UPM Mode Output Signals LCS 0 3 LBS 0 3 LGPL 0 5 GPCM Mode Output Signals LCS 0 3 LWE tLB...

Page 39: ...igure 23 Local Bus Signals GPCM UPM Signals for LCCR CLKDIV 4 DLL Bypass Mode LCLK UPM Mode Input Signal LUPWAIT tLBIXKH tLBIVKH tLBIVKH tLBIXKH tLBKHOZ T1 T3 UPM Mode Output Signals LCS 0 3 LBS 0 3 L...

Page 40: ...us Figure 24 Local Bus Signals GPCM UPM Signals for LCCR CLKDIV 4 DLL Enabled LSYNC_IN UPM Mode Input Signal LUPWAIT tLBIXKH2 tLBIVKH2 tLBIVKH1 tLBIXKH1 tLBKHOZ1 T1 T3 Input Signals LAD 0 31 LDP 0 3 U...

Page 41: ...tics Characteristic Symbol Condition Min Max Unit Input high voltage VIH OVDD 0 3 OVDD 0 3 V Input low voltage VIL 0 3 0 8 V Input current IIN 5 A Output high voltage VOH IOH 8 0 mA 2 4 V Output low v...

Page 42: ...for inputs and t first two letters of functional block reference state signal state for outputs For example tJTDVKH symbolizes JTAG device timing JT with respect to the time data input signals D reach...

Page 43: ...s the test access port timing diagram Figure 29 Test Access Port Timing Diagram TRST VM Midpoint Voltage OVDD 2 VM VM tTRST VM Midpoint Voltage OVDD 2 VM VM tJTDVKH tJTDXKH Boundary Data Outputs Bound...

Page 44: ...IH min to VIL max with a bus capacitance from 10 to 400 pF tI2KLKV 20 0 1 CB 250 ns 2 Pulse width of spikes which must be suppressed by the input filter tI2KHKL 0 50 ns 3 Input current each I O pin in...

Page 45: ...with respect to the time data input signals D reach the valid state V relative to the tI2C clock reference K going to the high H state or setup time Also tI2SXKL symbolizes I2C timing I2 for the time...

Page 46: ...provides the PCI AC timing specifications at 66 MHz Table 40 PCI DC Electrical Characteristics Parameter Symbol Test Condition Min Max Unit High level input voltage VIH VOUT VOH min or 2 OVDD 0 3 V Lo...

Page 47: ...tup and hold time is with respect to the rising edge of PORESET Table 42 PCI AC Timing Specifications at 33 MHz Parameter Symbol1 Min Max Unit Notes Clock to output valid tPCKHOV 11 ns 2 Output hold f...

Page 48: ...eescale Semiconductor PCI Figure 33 shows the PCI input AC timing diagram Figure 33 PCI Input AC Timing Diagram Figure 34 shows the PCI output AC timing diagram Figure 34 PCI Output AC Timing Diagram...

Page 49: ...in Max Unit Input high voltage VIH 2 0 OVDD 0 3 V Input low voltage VIL 0 3 0 8 V Input current IIN 5 A Output high voltage VOH IOH 8 0 mA 2 4 V Output low voltage VOL IOL 8 0 mA 0 5 V Output low volt...

Page 50: ...high voltage VIH 2 0 OVDD 0 3 V Input low voltage VIL 0 3 0 8 V Input current IIN 5 A Output high voltage VOH IOH 8 0 mA 2 4 V Output low voltage VOL IOL 8 0 mA 0 5 V Output low voltage VOL IOL 3 2 mA...

Page 51: ...VIL 0 3 0 8 V Input current IIN 5 A Output low voltage VOL IOL 8 0 mA 0 5 V 2 Output low voltage VOL IOL 3 2 mA 0 4 V 2 Notes 1 This table applies for pins IRQ 0 7 IRQ_OUT and MCP_OUT 2 IRQ_OUT and M...

Page 52: ...tNIKHOV 6 ns SPI outputs hold Master mode internal clock delay tNIKHOX 0 5 ns SPI outputs valid Slave mode external clock delay tNEKHOV 8 ns SPI outputs hold Slave mode external clock delay tNEKHOX 2...

Page 53: ...alling edge is the active edge Figure 36 shows the SPI timings in slave mode external clock Figure 36 SPI AC Timing in Slave Mode External Clock Diagram Figure 37 shows the SPI timings in master mode...

Page 54: ...ay TBGA See Section 18 1 Package Parameters for the MPC8349E TBGA and Section 18 2 Mechanical Dimensions for the MPC8349E TBGA 18 1 Package Parameters for the MPC8349E TBGA The package parameters are...

Page 55: ...nclature for the MPC8349E 672 TBGA package Notes 1 All dimensions are in millimeters 2 Dimensions and tolerances per ASME Y14 5M 1994 3 Maximum solder ball diameter measured parallel to datum A 4 Datu...

Page 56: ...0 J30 M31 P33 T34 I O OVDD PCI1_PAR P32 I O OVDD PCI1_FRAME M32 I O OVDD 5 PCI1_TRDY N29 I O OVDD 5 PCI1_IRDY M34 I O OVDD 5 PCI1_STOP N31 I O OVDD 5 PCI1_DEVSEL N30 I O OVDD 5 PCI1_IDSEL J31 I OVDD P...

Page 57: ...E5 G2 H6 E4 F3 G4 G3 H1 J2 L6 M6 H2 K6 L2 M4 N2 P4 R2 T4 P6 P3 R1 T2 AB5 AA3 AD6 AE4 AB4 AC2 AD3 AE6 AE3 AG4 AK5 AK4 AE2 AG6 AK3 AK2 AL2 AL1 AM5 AP5 AM2 AN1 AP4 AN5 AJ7 AN7 AM8 AJ9 AP6 AL7 AL9 AN8 I O...

Page 58: ...OP_IN AP22 I O OVDD LDP 2 AN22 I O OVDD LDP 3 AM22 I O OVDD LA 27 31 AK21 AP23 AN23 AP24 AK22 O OVDD LCS 0 3 AN24 AL23 AP25 AN25 O OVDD LWE 0 3 LSDDQM 0 3 LBS 0 3 AK23 AP26 AL24 AM25 O OVDD LBCTL AN26...

Page 59: ...GPIO1 10 GTM1_TGATE4 GTM2_TGATE3 F22 I O OVDD GPIO1 11 GTM1_TOUT4 GTM2_TOUT3 E22 I O OVDD USB Port 1 MPH1_D0_ENABLEN DR_D0_ENABLEN A26 I O OVDD MPH1_D1_SER_TXD DR_D1_SER_TXD B26 I O OVDD MPH1_D2_VMO_...

Page 60: ...D7_DRVVBUS DR_D15_IDPULLUP C31 I O OVDD MPH0_NXT DR_RX_ACTIVE_ID B32 I OVDD MPH0_DIR_DPPULLUP DR_RESET A32 I O OVDD MPH0_STP_SUSPEND DR_TX_READY A33 I O OVDD MPH0_PWRFAULT DR_RX_VALIDH C32 I OVDD MPH0...

Page 61: ...TSEC1_TX_EN B9 O LVDD1 TSEC1_TX_ER GPIO2 31 A16 I O OVDD Three Speed Ethernet Controller Gigabit Ethernet 2 TSEC2_COL GPIO1 21 C14 I O OVDD TSEC2_CRS GPIO1 22 D6 I O LVDD2 TSEC2_GTX_CLK A4 O LVDD2 TS...

Page 62: ...AM30 O OVDD I2 C interface IIC1_SDA AK29 I O OVDD 2 IIC1_SCL AP32 I O OVDD 2 IIC2_SDA AN31 I O OVDD 2 IIC2_SCL AM31 I O OVDD 2 SPI SPIMOSI AN32 I O OVDD SPIMISO AP33 I O OVDD SPICLK AK30 I O OVDD SPI...

Page 63: ...J13 Power for LBIU DLL 1 2 V AVDD4 GND A1 A34 C1 C7 C10 C11 C15 C23 C25 C28 D1 D8 D20 D30 E7 E13 E15 E17 E18 E21 E23 E25 E32 F6 F19 F27 F30 F34 G31 H5 J4 J34 K30 L5 M2 M5 M30 M33 N3 N5 P30 R5 R32 T5 T...

Page 64: ...29 AL30 AM20 AM23 AM24 AM26 AM28 AN11 AN13 PCI 10 100 Ethernet and other standard 3 3 V OVDD MVREF1 M3 I DDR reference voltage MVREF2 AD2 I DDR reference voltage Notes 1 This pin is an open drain sign...

Page 65: ...parameters select whether CLKIN or CLKIN 2 is driven out on the PCI_CLK_OUTn signals PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the sy...

Page 66: ...rmation on the clock subsystem The internal ddr_clk frequency is determined by the following equation ddr_clk csb_clk 1 RCWL DDRCM ddr_clk is not the external memory bus frequency ddr_clk passes throu...

Page 67: ...g frequency of the security core and USB modules does not exceed the respective values listed in this table 400 MHz 533 MHz 667 MHz Unit e300 core frequency core_clk 266 400 266 533 266 667 MHz Cohere...

Page 68: ...and the CFG_CLKIN_DIV configuration input signal select the ratio between the primary clock input CLKIN or PCI_CLK and the internal coherent system bus clock csb_clk Table 55 and Table 56 show the ex...

Page 69: ...in agent mode Input Clock Frequency MHz 2 16 67 25 33 33 66 67 csb_clk Frequency MHz Low 0010 2 1 133 Low 0011 3 1 100 200 Low 0100 4 1 100 133 266 Low 0101 5 1 125 166 333 Low 0110 6 1 100 150 200 Lo...

Page 70: ...if set high SPMF csb_clk Input Clock Ratio2 2 CLKIN is the input clock in host mode PCI_CLK is the input clock in agent mode Input Clock Frequency MHz 2 16 67 25 33 33 66 67 csb_clk Frequency MHz Low...

Page 71: ...k csb_clk Ratio VCO Divider1 1 Core VCO frequency core frequency VCO divider The VCO divider must be set properly so that the core VCO frequency is in the range of 800 1800 MHz 0 1 2 5 6 nn 0000 n PLL...

Page 72: ...33 200 400 33 200 400 33 200 400 624 0110 0100100 33 200 400 33 200 400 33 200 400 803 1000 0000011 33 266 400 33 266 400 33 266 400 823 1000 0100011 33 266 400 33 266 400 33 266 400 903 1001 0000011...

Page 73: ...2s2p R JMA 8 C W 1 3 Junction to ambient 2 m s on single layer board 1s R JMA 9 C W 1 3 Junction to ambient 2 m s on four layer board 2s2p R JMA 7 C W 1 3 Junction to board thermal R JB 3 8 C W 4 Junc...

Page 74: ...ies widely within the application For many natural convection and especially closed box applications the board temperature at the perimeter edge of the package is approximately the same as the local a...

Page 75: ...ient thermal resistance C W R JC junction to case thermal resistance C W R CA case to ambient thermal resistance C W R JC is device related and cannot be influenced by the user The user controls the t...

Page 76: ...h 408 567 8082 473 Sapena Ct 12 Santa Clara CA 95054 Internet www alphanovatech com International Electronic Research Corporation IERC 818 842 7277 413 North Moss St Burbank CA 91502 Internet www ctsc...

Page 77: ...orces that can lift the edge of the package or peel the package from the board Such peeling forces reduce the solder joint lifetime of the package The recommended maximum force on the top of the packa...

Page 78: ...ed Host Processor Hardware Specifications Rev 10 78 Freescale Semiconductor Thermal TJ TC R JC PD where TJ junction temperature C TC case temperature of the package C R JC junction to case thermal res...

Page 79: ...ages are derived directly from VDD through a low frequency filter scheme There are a number of ways to provide power reliably to the PLLs but the recommended solution is to provide five independent fi...

Page 80: ...the smaller chip capacitors These bulk capacitors should have a low ESR equivalent series resistance rating to ensure the quick response time They should also be connected to the power and ground pla...

Page 81: ...nal OVDD 105 C 21 6 Configuration Pin Multiplexing The MPC8349E power on configuration options can be set through external pull up or pull down resistors of 4 7 k on certain output pins see the custom...

Page 82: ...of signal quality or speed for the output pins 21 7 Pull Up Resistor Requirements The MPC8349E requires high resistance pull up resistors 10 k is recommended on open drain pins including I2 C pins the...

Page 83: ...TBGA parts for silicon Rev 1 x In Figure 42 JTAG Interface Connection updated with new figure In Section 23 Ordering Information replicated note from introduction In Section 23 1 Part Numbers Fully A...

Page 84: ...11 to 10 Changed classification of document to Technical Data 4 9 2005 Added Table 2 MPC8349E Typical I O Power Dissipation 3 8 2005 Table 1 Updated values for power dissipation that were TBD in Revi...

Page 85: ...ts including extended temperatures refer to the MPC8349E product summary page on our website listed on the back cover of this document or contact your local Freescale sales office Table 64 shows the S...

Page 86: ...ation 23 2 Part Marking Parts are marked as in the example shown in Figure 42 Figure 42 Freescale Part Marking for TBGA Devices MPCnnnnetppaaar core platform MHZ ATWLYYWW CCCCC TBGA MMMMM YWWLAZ Notes...

Page 87: ...MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications Rev 10 Freescale Semiconductor 87 Ordering Information THIS PAGE INTENTIONALLY LEFT BLANK...

Page 88: ...rectly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the desig...

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