Addendum List for Revision 7.1
MPC5607B Reference Manual Errata, Rev. 1
Freescale Semiconductor
6
Chapter 16, Enhanced Direct
Memory Access (eDMA),
page 330 (cont.)
Chapter 19, Crossbar Switch
(XBAR), throughout
chapter
Correct “two master ports” to “three master ports” as necessary.
Chapter 19, Crossbar Switch
(XBAR), page 379
Replace
Figure 19-1 (XBAR block diagram)
with the following.
Chapter 19, Crossbar Switch
(XBAR), page 379
Add the following row for eDMA to
Table 19-1 (XBAR switch ports for MPC5607B)
.
Chapter 19, Crossbar Switch
(XBAR), page 380
In
Section 19.4, Features
, add a bullet item for eDMA.
Table 1. MPC5607BRM Rev 7.1 Addenda (continued)
Location
Description
Table 16-26.Coherency model for method 2
Step
Action
1
Write 1b to theTCD.d_req bit.
Note: Should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a
future hardware activation of this channel. This stops the channel from
executing with a destination address (daddr) that was calculated using a
scatter/gather address (written in the next step) instead of a dlast final offset
value.
2
Write theTCD.dlast_sga field with the scatter/gather address.
3
Write 1b to the TCD.e_sg bit.
4
Read back the TCD.e_sg bit.
5
Test the TCD.e_sg request status:
• If e_sg = 1b, the dynamic link attempt was successful.
• If e_sg = 0b, read the 32 bit TCD dlast_sga field.
• If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not
succeed (the channel was already retiring).
• If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful
(the new TCD’s e_sg value cleared the e_sg bit).
CPU
Crossbar Switch
Flash
Master modules
Slave modules
CPU data
Internal
Peripheral
bridges
instructions
memory
SRAM
eDMA
Module
Port
Physical master ID
Type
Logical number
eDMA
Master
1
2
