Freescale Semiconductor MPC5565, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
19-36 Freescale Semiconductor
The transitions are described in Table 19-17 .
State transitions from RUNNING to STOPPED occur on the next frame boundary if a transfer is in
progress, or on the next system clock cycle if no transfers are in progress.
19.4.3 Serial Peripheral Interface (SPI) Configuration
The SPI configuration transfers data serially using a shift register and a selection of programmable transfer
attributes. The DSPI is in SPI configuration when the DCONF field in the DSPI
x _MCR is 0b00. The SPI
frames can be from 4 to 16 bits long. The data to be transmitted can come from queues stored in RAM
external to the DSPI. Host software or an eDMA controller can transfer the SPI data from the queues to a
first-in first-out (FIFO) buffer. The received data is stored in entries in the receive FIFO (RX FIFO) buffer.
Host software or an eDMA controller transfers the received data from the RX FIFO to memory external
to the DSPI.
The FIFO buffer operations are described in Section 19.4.3.4, “Transmit First In First Out (TX FIFO)
Buffering Mechanism ,” and Section 19.4.3.5, “Receive First In First Out (RX FIFO) Buffering
Mechanism .”
The interrupt and DMA request conditions are described in Section 19.4.9, “Interrupts/DMA Requests .”
The SPI configuration supports two module-specific modes; master mode and slave mode. The FIFO
operations are similar for the master mode and slave mode. The main difference is that in master mode the
DSPI initiates and controls the transfer according to the fields in the SPI command field of the TX FIFO
entry. In slave mode the DSPI only responds to transfers initiated by a bus master external to the DSPI and
the SPI command field of the TX FIFO entry is ignored.
19.4.3.1 SPI Master Mode
In SPI master mode the DSPI initiates the serial transfers by controlling the serial communications clock
(SCK
x ) and the peripheral chip select (PCS x ) signals. The SPI command field in the executing TX FIFO
entry determines which CTARs are used to set the transfer attributes and which PCS x signal to assert. The
Table 19-17. State Transitions for Start and Stop of DSPI Transfers
Transition # Current State Next State Description
0 RESET STOPPED Generic power-on-reset transition
1 STOPPED RUNNING The DSPI starts (transitions from STOPPED to RUNNING) when all
of the following conditions are true:
• EOQF bit is clear
• Debug mode is unselected or the FRZ bit is clear
• HALT bit is clear
2 RUNNING STOPPED The DSPI stops (transitions from RUNNING to STOPPED) after the
current frame for any one of the following conditions:
• EOQF bit is set
• Debug mode is selected and the FRZ bit is set
• HALT bit is set