Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-39
Table 18-27. ADC n _CR Field Descriptions
Field Description
0
ADC n _
EN
ADC n enable. Enables ADC n to perform A/D conversions. Refer to Section 18.4.5.1, “Enabling and Disabling the
on-chip ADCs ,” for details.
0 ADC is disabled. Clock supply to ADC0/1 is stopped.
1 ADC is enabled and ready to perform A/D conversions.
Note: The bias generator circuit inside the ADC ceases functioning when both ADC0_EN and ADC1_EN bits are
negated.
Note: Conversion commands sent to a disabled ADC are ignored by the ADC control hardware.
Note: When the ADC n _EN status is changed from asserted to negated, the ADC clock does not stop until it reaches
its low phase.
1–3 Reserved.
4
ADC n _
EMUX
ADC n external multiplexer enable. When ADC n _EMUX is asserted, the MA pins output digital values to the external
channel number selected to convert external multiplexer inputs. Refer to Section 18.4.6, “Internal/External
Multiplexing ,” for a detailed description about how ADC n _EMUX affects channel number decoding.
0 External multiplexer disabled; no external multiplexer channels can be selected.
1 External multiplexer enabled; external multiplexer channels can be selected.
Note: Both ADC n _EMUX bits must not be asserted at the same time.
Note: The ADC n _EMUX bit must only be written when the ADC n _EN bit is negated. ADC n _EMUX can be set during
the same write cycle used to set ADC n _EN.
5–10 Reserved.
11–15
ADC n _
CLK_PS
[0:4]
ADC n clock prescaler. The ADC n _CLK_PS field controls the system clock divide factor for the ADC n clock as in
Table 18-28 . Refer to Section 18.4.5.2, “ADC Clock and Conversion Speed ,” for details about how to set
ADC0/1_CLK_PS.
The ADC
n _CLK_PS field must only be written when the ADC n _EN bit is negated. This field can be configured during
the same write cycle used to set ADC n _EN.
Table 18-28. System Clock Divide Factor for ADC Clock
ADC n _CLK_PS[0:4]
System Clock
Divide Factor
0b00000 2
0b00001 4
0b00010 6
0b00011 8
0b00100 10
0b00101 12
0b00110 14
0b00111 16
0b01000 18
0b01001 20
0b01010 22
0b01011 24