Freescale Semiconductor MPC5565, Reference Manual

Page: 706 / 1153

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-7
If the null message transmission is aborted, the eQADC completes the abort procedure before
halting future command transfers from any CFIFO. The message of the CFIFO that caused the
abort of the previous serial transmission is only transmitted after stop mode exits.
• Command transfer is in progress.
The eQADC completes the transfer and update CFIFO status before halting future command
transfers from any CFIFO.
Command transfers to the external device are considered completed when the serial transmission
of the command is completed. If valid data (conversion result or data read from an ADC register)
is received at the end of a serial transmission, it is not sent to an RFIFO until stop mode exits. The
CFIFO status bits are still updated after the completion of the serial transmission, therefore, after
stop mode entry request is detected, the eQADC status bits stop changing several system clock
cycles after the on-going serial transmission completes.
If the command message transmission is aborted, the eQADC completes the abort procedure before
halting future command transfers from any CFIFO. The message of the CFIFO that caused the
abort of the previous serial transmission are transmitted only after stop mode exits.
• Command/null message transfer through serial interface was aborted but next serial transmission
did not start.
If the stop mode entry request is detected between the time a previous serial transmission was
aborted and the start of the next transmission, the eQADC completes the abort procedure before
halting future command transfers from any CFIFO. The message of the CFIFO that caused the
abort of the previous serial transmission is transferred only after stop mode is exited.
18.2 External Signal Description
These signals are external to the eQADC module, but may or may not be physical pins. Refer to Chapter 2,
“Signal Description ” for a complete list of all physical pins and signals.
Table 18-1. eQADC External Signals
Function Description
I/O
Type
Status
During
Reset
1
Status
After
Reset
2
Type Package
AN[0]_
DAN0+ Single-ended analog input 0
Positive terminal differential input I I / — AN[0]/ — Analog 496
324
AN[1]_
DAN0- Single-ended analog input 1
Negative terminal differential input I I / — AN[1]/ — Analog 496
324
AN[2]_
DAN1+ Single-ended analog input 2
Positive terminal differential input I I / — AN[2] / — Analog 496
324
AN[3]_
DAN1- Single-ended analog input 3
Negative terminal differential input I I / — AN[3] / — Analog 496
324