Freescale Semiconductor MPC5565, Reference Manual

Page: 704 / 1153

Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 18-5
18.1.4 Modes of Operation
This section describes the operating modes of the eQADC.
18.1.4.1 Normal Mode
This is the default operational mode when the eQADC is not in background debug or stop mode.
18.1.4.2 Debug Mode
Upon a debug mode entry request, eQADC behavior varies according to the status of the DBG field in
Section 18.3.2.1, “eQADC Module Configuration Register (EQADC_MCR) .” If DBG is programmed to
0b00, the debug mode entry request is ignored. If DBG is programmed to 0b10 or to 0b11, the eQADC
enters debug mode. In case the eQADC SSI is enabled, the free running clock (FCK) output to external
device does not stop when DBG is programmed to 0b11, but FCK stops in low phase, when DBG is
programmed to 0b10.
During debug mode, the eQADC does not transfer commands from any CFIFOs, no null messages are
transmitted to the external device, no data is returned to any RFIFO, no hardware trigger event is captured,
and all eQADC registers can be accessed as in normal mode. Access to eQADC registers implies that
CFIFOs can still be triggered using software triggers, because no scheme is implemented to write-protect
registers during debug mode. eDMA and interrupt requests continue to be generated as in normal mode.
If at the time the debug mode entry request is detected, there are commands in the ADC that were already
under execution, these commands are completed but the generated results, if any, are not sent to the
RFIFOs until debug mode is exited. Commands that have not begun to execute are not executed until after
exiting debug mode. The clock with an on-chip ADC stops, during its low phase, after the ADC stops
executing commands. The time base counter only stops after all on-chip ADCs stop executing commands.
When exiting debug mode, the eQADC relies on the FIFO control unit and on the CFIFO status to
determine the next command entry to transfer.
The eQADC internal behavior after the debug mode entry request is detected differs depending on the
status of command transfers.
• No command transfer is in progress.
The eQADC immediately halts future command transfers from any CFIFO.
If a null message is being transmitted, eQADC completes the serial transmission before halting
future command transfers. If valid data (conversion result or data read from an ADC register) is
received by the result format and calibration submodule at the end of transmission, this data is not
sent to an RFIFO until debug mode is exited.
If the null message transmission is aborted, the eQADC completes the abort procedure before
halting future command transfers from any CFIFO. The message of the CFIFO that caused the
abort of the previous serial transmission is transmitted only after exiting debug mode.
• Command transfer is in progress.
eQADC completes the transfer and updates CFIFO status before halting future command transfers
from any CFIFO.