Freescale Semiconductor MPC5565, Reference Manual

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Flash Memory
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 13-37
13.5 Document Revision History
Table 13-18. Changes Between MPC5565RM Revisions 0.1 and 1
In the Overview section, made this change:
• From: “...and a 256-bit read data interface to flash memory. If enabled, the Flash BIU contains a two-entry, 256-bit prefetch
buffer and a prefetch controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer
hits allow no-wait responses. Normal flash array accesses are registered in the FBIU and are forwarded to the system bus
on the following cycle, . .”
• To: “...and a 256-bit read data interface from the flash memory array. If enabled, the Flash BIU contains a two-entry prefetch
buffer, each entry containing 256 bits of data, and an associated controller that prefetches sequential lines of data from the
flash array into the buffer. Prefetch buffer hits support zero-wait responses. Normal flash array accesses (i.e. those
accesses that do not hit in the prefetch buffers) are registered in the FBIU and are forwarded to the system bus on the
following cycle,...”
Section 13.1.3, “Features”: Changed 2nd bulletted list, fourth bullet to “Page program size of 256 bits allows programming
from one to four consecutive 64-bit doublewords within a page.”