Freescale Semiconductor MPC5565, Reference Manual

Page: 49 / 1153

Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
1-14 Freescale Semiconductor
three regions via dedicated calibration chip selects (two chip selects multiplexed with two address bits),
along with programmed region-specific attributes.
1.4.8 System Integration Unit (SIU)
The device’s system integration unit (SIU) controls MCU reset configuration, pad configuration, external
interrupt, general-purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation.
The reset configuration module contains the external pin boot configuration logic. The pad configuration
module controls the static electrical characteristics of I/O pins. The GPIO module provides uniform and
discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring
of internal and external reset sources, and drives the RSTOUT pin. The SIU is accessed by the e200z6 core
through the crossbar switch.
1.4.9 Error Correction Status Module (ECSM)
The error correction status module (ECSM) provides status information regarding platform memory errors
reported by error-correcting codes.
1.4.10 Flash Memory
The MPC5565 provides 2 MB of programmable, non-volatile, flash memory storage. Non-volatile
memory (NVM) can be used for instruction and/or data storage.
The flash memory has a flash bus interface unit (FBIU) that connects the system bus to a dedicated flash
memory array controller. The FBIU supports a 64-bit data bus width at the system bus port, and a 256-bit
read data interface to flash memory. The FBIU contains two 256-bit prefetch buffers, and a prefetch
controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits
allow no-wait responses. Normal flash array accesses are registered in the FBIU and are forwarded to the
system bus on the following cycle, incurring three wait-states. Prefetch operations can be automatically
controlled, as well as restricted to servicing a single bus master. Prefetches can also require a trigger for
instruction or data accesses.
1.4.11 Cache
The e200z6 core supports an eight-KB, two-way set-associative, unified (instruction and data) cache with
a 32-byte line size. The cache improves system performance by providing low-latency data to the e200z6
instruction and data pipelines, which decouples processor performance from system memory performance.
The cache is virtually indexed and physically tagged. The e200z6 does not provide hardware support for
cache coherency in a multi-master environment. Software must be designed to maintain cache coherency
with other possible bus masters.
Both instruction and data accesses are performed using a single bus connected to the cache. The processor
uses virtual addresses to index the cache array. The memory management unit (MMU) provides the
virtual-to-physical address conversion to perform the cache tag compare. The MMU can pass the virtual
addresses to the cache as the physical address without the conversion. If the physical address matches a
valid cache tag entry, the access hits in the cache. For a read operation, the cache supplies the data to the