Freescale Semiconductor MPC5565, Reference Manual

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External Bus Interface (EBI)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 12-25
The upper write/byte enable (WE/BE[0]) indicates that the upper eight bits of the data bus (DATA[0:7])
contain valid data during a write/read cycle. The lower write/byte enable (WE/BE[1]) indicates that the
lower eight bits of the data bus (DATA[8:15]) contain valid data during a write/read cycle.
The write/byte enable lines affected in a transaction are shown in Table 12-13 . Only big endian byte
ordering is supported by the EBI.
12.4.1.15 Configurable Bus Speed Clock Modes
The EBI supports configurable bus speed clock modes. Refer to Section 12.1.4.4, “Configurable Bus
Speed Modes ,” for more details on this feature.
12.4.1.16 Stop and Module Disable Modes for Power Savings
Refer to Section 12.1.4, “Modes of Operation ,” for a description of the power saving modes.
12.4.1.17 Optional Automatic CLKOUT Gating
The EBI has the ability to hold the external CLKOUT pin high when the EBI’s internal master state
machine is idle and no requests are pending. The EBI outputs a signal to the pads logic in the MCU to
disable CLKOUT. This feature is disabled out of reset, and can be enabled or disabled by the ACGE bit in
the EBI_MCR.
Table 12-13. Write/Byte Enable Signals Function -- 324 BGA
Transfer
Size
TSIZ[0:1]
1
1
TSIZ is not available on the MPC5565.
Address 16-Bit Port Size
2
2
Also applies when DBM = 1 for 16-bit data bus mode.
A[30] A[31] WE/BE[0] WE/BE[1]
Byte 01 0 0 X —
01 0 1 — X
01 1 0 X —
01 1 1 — X
16-bit 10 0 0 X X
10 1 0 X X
32-bit 00 0 0 X
3
3
This case consists of two 16-bit external transactions, but for both
transactions the WE/BE[0:1] signals are the only WE/BE signals
affected.
NOTE: “X” indicates that valid data is transferred on these bits.
X
3
Burst 00 0 0 X X