Freescale Semiconductor MPC5565, Reference Manual

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Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
1-12 Freescale Semiconductor
Vectored and auto-vectored interrupts are supported by the CPU. Vectored interrupt supports unique
interrupt handlers invoked with no software overhead for multiple interrupt sources.
The signal processing extension (SPE) APU supports vector instructions (SIMD) operating on 16- and
32-bit fixed-point data types, as well as 32-bit IEEE
®
-754 single-precision floating-point formats, and
supports single-precision floating-point operations in a pipelined fashion. The 64-bit general-purpose
register file is used for source and destination operands, and there is a unified storage model for
single-precision floating-point data types of 32-bits and the normal integer type. Low latency fixed-point
and floating-point add, subtract, multiply, divide, compare, and conversion operations are provided, and
most operations can be pipelined.
The CPU includes support for Variable Length Encoding (VLE) instruction enhancements that have
modified instruction set that uses a combination of 16- and 32-bit instructions from the classic Power
Architecture instruction. This reduces the code size without noticeably affecting performance. The classic
Power Architecture instruction set and VLE instruction set are available concurrently. Regions of the
memory map are designated as PPC or VLE using an additional configuration bit in each table look-aside
buffer (TLB) entry in the MMU.
1.4.2 System Bus Crossbar Switch (XBAR)
The system bus’ multi-port crossbar (XBAR) switch supports simultaneous connections between three
master ports and five slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus
width on all master and slave ports.
The crossbar allows concurrent transactions from any master port to any slave port. It is possible to use all
master ports and slave ports at the same time as a result of independent master requests. If a slave port is
simultaneously requested by more than one master port, arbitration logic selects the highest priority master
and grants it ownership of the slave port. All other masters requesting that slave port must wait until the
higher priority master completes its transactions. By default, masters requests’ have equal priority and are
granted access to a slave port in round-robin fashion based on the last master ID granted access.
1.4.3 Enhanced Direct Memory Access (eDMA)
The enhanced direct memory access (eDMA) controller is a second-generation module capable of
performing complex data movements via 32 programmable channels, with minimal intervention from the
CPU. The hardware microarchitecture includes a DMA engine which performs source and destination
address calculations, and the actual data movement operations, along with an SRAM-based memory
containing the transfer control descriptors (TCD) for the channels. This implementation is used to
minimize the overall module size.