Freescale Semiconductor MPC5565, Reference Manual

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Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 1-11
1.4 Detailed Features
The following sections provide detailed information about each of the on-chip modules.
1.4.1 e200z6 Core Overview
The device uses the e200z6 core explained in detail in the e200z6 PowerPC
TM
Core Reference Manual .
The e200z6 CPU uses a seven-stage pipeline for instruction execution:
• Instruction fetch 1
• Instruction fetch 2
• Instruction decode and register file read
• Execute 1
• Execute 2 and memory access 1
• Execute 3 and memory access 2
• Register writeback
The operation of the pipeline stages overlap so that most instructions execute in a single-clock.
The integer execution unit consists of a 32-bit arithmetic unit (AU), a logic unit (LU), a 32-bit barrel
shifter, a mask-insertion unit (MIU), a condition register manipulation unit (CRU), a count-leading-zeros
unit (CLZ), a 32 x 32 hardware multiplier array, result feed-forward hardware, and support hardware for
division.
Most arithmetic and logical operations are executed in a single cycle with the exception of multiply and
divide instructions, which are implemented with a pipelined hardware array. The CLZ unit operates in a
single clock cycle.
The instruction unit contains an incremental program counter (PC) and a dedicated branch address adder
to minimize delays during change of flow operations. Sequential prefetching is performed to ensure a
supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate
taken branches. Prefetched instructions are placed into an instruction buffer capable of holding six
sequential instructions and two branch target instructions.
Branch target addresses are calculated in parallel with branch instruction decode, resulting in execution
time of three clocks. Conditional branches which are not taken execute in a single clock. Branches with
successful look-ahead and target prefetching have an effective execution time of one clock.
Memory load and store operations are provided for byte, halfword, word (32-bits), and doubleword
(64-bits) data with automatic zero or sign extension of byte and halfword load data. These instructions can
be pipelined to allow effective single cycle throughput. Load and store multiple word instructions allow
low overhead context save and restore operations. The load/store unit contains a dedicated effective
address adder to allow effective address generation to be optimized.
The condition register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture technology. The condition register consists of eight 4-bit fields that reflect the
results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical
instructions, and provide a mechanism for testing and branching.