Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 11-23
process, the system clock frequency is not well defined and can exceed the maximum system frequency
thereby violating the system clock timing specifications (when changing MFD and PREDIV, this is
avoided by following the procedure detailed in
Section 11.4.3, “Clock Configuration ”). Because this
condition can arise during unexpected loss of lock events, it is recommended to use the loss of lock reset
functionality, Refer to
Section 11.4.2.5.1, “FMPLL Loss-of-Lock Reset ,” below. However, LOLRE must
be cleared while changing the MFD otherwise a reset occurs.
After the FMPLL has relocked, the LOCK bit is set. The LOCKS bit remains cleared if the loss of lock
was unexpected. The LOCKS bit is set to 1 when the loss of lock was caused by changing the MFD.
11.4.2.5.1 FMPLL Loss-of-Lock Reset
The FMPLL provides the ability to assert reset when a loss of lock condition occurs by programming the
FMPLL_SYNCR[LOLRE] bit. Reset is asserted if LOLRE is set and loss of lock occurs. Because the
FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS] bits are reinitialized after reset, the system reset
status register (SIU_RSR) must be read to determine that a loss of lock condition occurred.
To exit reset, the reference must be present and the FMPLL must acquire lock. In bypass mode, the FMPLL
cannot lock. Therefore a loss of lock condition cannot occur, and LOLRE has no effect.
11.4.2.5.2 FMPLL Loss-of-Lock Interrupt Request
The FMPLL provides the ability to request an interrupt when a loss of lock condition occurs by
programming the FMPLL_SYNCR[LOLIRQ] bit. An interrupt is requested by the FMPLL if LOLIRQ is
set and loss of lock occurs.
In bypass mode, the FMPLL cannot lock. Therefore a loss of lock condition cannot occur, and the LOLIRQ
bit has no effect.
11.4.2.6 Loss-of-Clock Detection
The FMPLL continuously monitors the reference and feedback clocks. In the event either of the clocks fall
below a threshold frequency, the system reports a loss of clock condition. The user can enable a feature to
have the FMPLL switch the system clocks to a backup clock in the event of such a failure. Additionally,
the user can select to have the system enter reset, assert an interrupt request, or do nothing if/when the
FMPLL reports this condition.
11.4.2.6.1 Alternate/Backup Clock Selection
If the user enables loss of clock by setting FMPLL.SYNCR[LOCEN] = 1, then the FMPLL transitions
system clocks to a backup clock source in the event of a clock failure as per
Table 11-8 .
If loss of clock is enabled and the reference clock is the source of the failure, the FMPLL enters self-clock
mode (SCM). The exact frequency during self-clock mode operation is indeterminate due to process,
voltage, and temperature variation but is guaranteed to be below the maximum system frequency. If the
FMPLL clocks have failed, the FMPLL transitions the system clock source to the reference clock.