Freescale Semiconductor MPC5565, Reference Manual

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Frequency Modulated Phase Locked Loop and System Clocks (FMPLL)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
11-22 Freescale Semiconductor
11.4.2.1 Input Clock Frequency
The FMPLL is designed to operate over an input clock frequency range as determined by the operating
mode. The operating ranges for each mode are given in
Table 11-7 .
11.4.2.2 Reduced Frequency Divider (RFD)
The RFD can be used for reducing the FMPLL system clock frequency. To protect the system from
frequency overshoot during the PLL lock detect phase, the RFD must be programmed to be greater than
or equal to 1 when changing MFD or PREDIV or when enabling frequency modulation.
11.4.2.3 Programmable Frequency Modulation
The FMPLL provides for frequency modulation of the system clock. The modulation is applied as a
triangular waveform with modulation depth and rate controlled by fields in the FMPLL_SYNCR. The
modulation depth can be set to +/-1% or +/-2% of the system frequency. The modulation rate is dependent
on the reference clock frequency.
Complete details for configuring the programmable frequency modulation is given in Section 11.4.3.2,
“Programming System Clock Frequency with Frequency Modulation .”
11.4.2.4 FMPLL Lock Detection
A pair of counters monitor the reference and feedback clocks to determine when the system has acquired
frequency lock. After the FMPLL has locked, the counters continue to monitor the reference and feedback
clocks and reports if/when the FMPLL has lost lock. The FMPLL_SYNCR provides the flexibility to
select whether to generate an interrupt, assert system reset, or do nothing in the event that the FMPLL loses
lock. Refer to
Section 11.3.1.1, “Synthesizer Control Register (FMPLL_SYNCR) for details.
When the frequency modulation is enabled, the loss of lock continues to function as described but with the
lock and loss of lock criteria reduced to ensure that false loss of lock conditions are not detected.
In bypass mode, the FMPLL cannot lock since the FMPLL is disabled.
11.4.2.5 FMPLL Loss-of-Lock Conditions
After the FMPLL acquires lock after reset, the FMPLL_SYNSR[LOCK] and FMPLL_SYNSR[LOCKS]
status bits are set. If the MFD is changed or if an unexpected loss of lock condition occurs, the LOCK and
LOCKS status bits are negated.
While the FMPLL is in an unlocked condition, the system clocks continue
to be sourced from the FMPLL as the FMPLL attempts to re-lock. Consequently, during the re-locking
Table 11-7. Input Clock Frequency
Mode Symbol Input Frequency Range
Crystal reference
External reference F
ref_crystal
F
ref_ext
8–20 MHz
Bypass F
extal
0–132 MHz
Dual-controller (1:1) F
ref_1:1
25–66 MHz