Freescale Semiconductor MPC5565, Reference Manual

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Introduction
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 1-3
1.2 Features
This section provides a high-level description of the features found in the MPC5565.
• Operating parameters
— Fully static operation, up to 132 MHz
— –40 to 150
°
C junction temperature
— Low-power design
– Less than 1.2 Watts power dissipation
– Designed for dynamic power management of core and peripherals
– Software-controlled clock gating of peripherals
– Separate power supply for stand-by operation for portion of internal SRAM
— Fabricated in 0.13
μ
m process
— 1.5 V internal logic
— Input and output pins with 3.0
–
5.25 V range
– 35% or 65% V
DDEH
CMOS switch levels (with hysteresis)
– Selectable hysteresis
– Selectable slew rate control
— External bus support 1.62
–
3.6 V operation and Nexus pins support 2.5–3.6 V operation
– Selectable drive strength control
– Unused pins configurable as GPIO
— Designed with EMI reduction techniques
– Frequency modulated phase-locked loop
– On-chip bypass capacitance
– Selectable slew rate and drive strength
• High-performance e200z6 core processor
— 32-bit CPU built on Power Architecture
™
technology
— Freescale Variable Length Encoding (VLE) enhancements for code size footprint reduction
— Thirty-two 64-bit general-purpose registers (GPRs)
— Memory management unit (MMU) with 32-entry fully-associative translation look-aside
buffer (TLB)
— Branch processing unit
— Fully pipelined load/store unit
— Eight KB unified cache with line locking
– Two-way set associative
– Two 32-bit fetches per clock
– Eight-entry store buffer
– Way locking
– Supports assigning cache as instruction or data only on a per-way basis