Freescale Semiconductor MPC5565, Reference Manual

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Crossbar Switch (XBAR)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
7-4 Freescale Semiconductor
7.2.1 Register Descriptions
There are two registers for each slave port of the XBAR. The registers can only be accessed in supervisor
mode using 32-bit accesses.
The slave SGPCR also features a bit (RO), which when written with a 1, prevents all slave registers for
that port from being written to again until a reset occurs. The registers remain readable, but future write
attempts have no effect on the registers and are terminated with an error response.
The difference in numerical values of XBAR Master Port and Master ID is shown in Table 7-3 .
7.2.1.1 Master Priority Registers (XBAR_MPR n )
The XBAR_MPR for a slave port sets the priority of each master port when operating in fixed priority
mode. They are ignored in round-robin priority mode unless more than one master has been assigned high
priority by a slave.
NOTE
Masters must be assigned unique priority levels.
Base + 0x0704–
Base +
0x070F
— Reserved —
Base + 0x0710 XBAR_SGPCR7 General-purpose control register for slave port 7 32
Base + 0x0714–
Base + 0x0003_FFFF
— Reserved —
Table 7-3. XBAR Switch Ports
Module
Port
Master ID
Type Number
e200z6 core—CPU instruction / data Master 0 0
e200z6—Nexus Master 0 1
eDMA Master 1 2
External bus interface Master 2 3
Flash Slave 0 —
External bus interface Slave 1 —
Internal SRAM Slave 3 —
Peripheral bridge A (PBRIDGE_A) Slave 6 —
Peripheral bridge B (PBRIDGE_B) Slave 7 —
Table 7-2. XBAR Register Memory Map (continued)
Address Register Name Register Description Bits