MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor
3-1
Chapter 3
e200z6 Core Complex
3.1
Introduction
The core complex of the device consists of the e200z6 core, an 8 KB unified cache memory, a 32-entry
memory management unit (MMU), a Nexus class 3 block, and a bus interface unit (BIU). The e200z6 core
is the central processing unit (CPU) in the device. The e200z6 core is part of the family of CPU cores that
implement versions built on the Power Architecture
™
embedded category.
The host processor core of the device complies with the Power Architecture embedded category, which is
100 percent user mode compatible with the original Power PC
™
user instruction set architecture (UISA).
However, in the Power Architecture definition, the original floating-point resources (used by a SIMD
design supporting single-precision vector and single-precision scalar operations) are provided that share
the GPRs defined for integer instructions.
Refer to the
e200z6 PowerPC
TM
Core Reference Manual
for more information on the e200z6 core.
3.1.1
Block Diagram
shows a block diagram of the e200z6 core complex.
Summary of Contents for MPC5565
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