3.7.1.6 ADC Reference Options
The ADC supports the following references:
• VREFH/VREFL - connected as the primary reference option
• 1.2 V VREF_OUT - connected as the V
ALT
reference option
ADCx_SC2[REFSEL] bit selects the voltage reference sources for ADC. Refer to
REFSEL description in ADC chapter for more details.
3.7.1.7 VBAT connection to ADC input channel
The VBAT supply input can be converted as a single ended input to ADC1 Channel 22.
When VBAT is greater than the selected voltage reference, the conversion result will
show a saturated result (~0xFFFF in 16-bit operation). When measuring the VBAT
voltage level the ADC should be configured for a long sample time
(ADC1_CFG1[ADLSMP]=1, ADC1_CFG2[ADLSTS]=00).
3.7.1.8 ADC triggers
The ADC supports both software and hardware triggers. The primary hardware
mechanism for triggering the ADC is the PDB. The PDB itself can be triggered by other
peripherals. For example: RTC (Alarm, Seconds) signal is connected to the PDB. The
PDB input trigger can receive the RTC (alarm/seconds) trigger forcing ADC conversions
in run mode (where PDB is enabled). On the other hand, the ADC can conduct
conversions in low power modes, not triggered by PDB. This allows the ADC to do
conversions in low power mode and store the output in the result register. The ADC
generates interrupt when the data is ready in the result register that wakes the system
from low power mode. The PDB can also be bypassed by using the ADCxTRGSEL bits
in the SIM_SOPT7 register.
Table 3-42. ADC Alternate trigger options
SIM_SOPT7[ADCxTRGSEL]
Selected source
0000
PDB external trigger pin input (PDB0_EXTRG)
0001
CMP0 output
0010
CMP1 output
0011
Reserved
0100
PIT trigger 0
0101
PIT trigger 1
Table continues on the next page...
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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