Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FTMx_EXTTRIG field descriptions
Field
Description
31–8
Reserved
This field is reserved.
7
TRIGF
Channel Trigger Flag
Set by hardware when a channel trigger is generated. Clear TRIGF by reading EXTTRIG while TRIGF is
set and then writing a 0 to TRIGF. Writing a 1 to TRIGF has no effect.
If another channel trigger is generated before the clearing sequence is completed, the sequence is reset
so TRIGF remains set after the clear sequence is completed for the earlier TRIGF.
0
No channel trigger was generated.
1
A channel trigger was generated.
6
INITTRIGEN
Initialization Trigger Enable
Enables the generation of the trigger when the FTM counter is equal to the CNTIN register.
0
The generation of initialization trigger is disabled.
1
The generation of initialization trigger is enabled.
5
CH1TRIG
Channel 1 Trigger Enable
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0
The generation of the channel trigger is disabled.
1
The generation of the channel trigger is enabled.
4
CH0TRIG
Channel 0 Trigger Enable
Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
0
The generation of the channel trigger is disabled.
1
The generation of the channel trigger is enabled.
3
CH5TRIG
Channel 5 Trigger Enable
Table continues on the next page...
Chapter 38 FlexTimer Module (FTM)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
849
