Table 3-25. WDOG clock connections (continued)
Module clock
Chip clock
Alt Clock
Bus Clock
Fast Test Clock
Bus Clock
System Bus Clock
Bus Clock
3.3.11.2 WDOG low-power modes
This table shows the WDOG low-power modes and the corresponding chip low-power
modes.
Table 3-26. WDOG low-power modes
Module mode
Chip mode
Wait
Wait, VLPW
Stop
Stop, VLPS
Power Down
LLS, VLLSx
3.4 Clock modules
3.4.1 MCG Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Chapter 3 Chip Configuration
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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