37.3.6 Channel n Status register (PDBx_CHnS)
Address: 4003_6000h base + 14h (40d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnS field descriptions
Field
Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–16
CF
PDB Channel Flags
The CF[
m
] bit is set when the PDB counter matches the CH
n
DLY
m
. Write 0 to clear these bits.
15–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–0
ERR
PDB Channel Sequence Error Flags
Only the lower M bits are implemented in this MCU.
0
Sequence error not detected on PDB channel's corresponding pre-trigger.
1
Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered
for a conversion by one pre-trigger from PDB channel
n
. When one conversion, which is triggered by
one of the pre-triggers from PDB channel
n
, is in progress, new trigger from PDB channel's
corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0’s to clear the
sequence error flags.
37.3.7 Channel n Delay 0 register (PDBx_CHnDLY0)
Address: 4003_6000h base + 18h (40d × i), where i=0d to 1d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PDBx_CHnDLY0 field descriptions
Field
Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15–0
DLY
PDB Channel Delay
Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the
counter is equal to DLY. Reading this field returns the value of internal register that is effective for the
current PDB cycle.
Memory map and register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
806
Freescale Semiconductor, Inc.
