ADCx_CFG1 field descriptions
Field
Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
ADLPC
Low-Power Configuration
Controls the power configuration of the successive approximation converter. This optimizes power
consumption when higher sample rates are not required.
0
Normal power configuration.
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
6–5
ADIV
Clock Divide Select
Selects the divide ratio used by the ADC to generate the internal clock ADCK.
00
The divide ratio is 1 and the clock rate is input clock.
01
The divide ratio is 2 and the clock rate is (input clock)/2.
10
The divide ratio is 4 and the clock rate is (input clock)/4.
11
The divide ratio is 8 and the clock rate is (input clock)/8.
4
ADLSMP
Sample Time Configuration
Selects between different sample times based on the conversion mode selected. This field adjusts the
sample period to allow higher impedance inputs to be accurately sampled or to maximize conversion
speed for lower impedance inputs. Longer sample times can also be used to lower overall power
consumption if continuous conversions are enabled and high conversion rates are not required. When
ADLSMP=1, the long sample time select bits, (ADLSTS[1:0]), can select the extent of the long sample
time.
0
Short sample time.
1
Long sample time.
3–2
MODE
Conversion mode selection
Selects the ADC resolution mode.
00
When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with
2's complement output.
01
When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion
with 2's complement output.
10
When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion
with 2's complement output
11
When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion
with 2's complement output
1–0
ADICLK
Input Clock Select
Selects the input clock source to generate the internal clock, ADCK. Note that when the ADACK clock
source is selected, it is not required to be active prior to conversion start. When it is selected and it is not
active prior to a conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at the
start of a conversion and deactivated when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated.
00
Bus clock
01
Alternate clock 2 (ALTCLK2)
10
Alternate clock (ALTCLK)
11
Asynchronous clock (ADACK)
Chapter 33 Analog-to-Digital Converter (ADC)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
701
