PORTx_DFER field descriptions (continued)
Field
Description
The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is
reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the
digital filter of the same number as the field.
0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
11.5.6 Digital Filter Clock Register (PORTx_DFCR)
This register is read only for ports that do not support a digital filter.
The digital filter configuration is valid in all digital pin muxing modes.
Address: Base a C4h offset
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PORTx_DFCR field descriptions
Field
Description
31–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
CS
Clock Source
The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the
digital input filters. Changing the filter clock source must be done only when all digital filters are disabled.
0
Digital filters are clocked by the bus clock.
1
Digital filters are clocked by the 1-kHz LPO clock.
11.5.7 Digital Filter Width Register (PORTx_DFWR)
This register is read only for ports that do not support a digital filter.
The digital filter configuration is valid in all digital pin muxing modes.
Chapter 11 Port Control and Interrupts (PORT)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
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