Table 6-3. Flash Option Register Bit Definitions (continued)
Bit
Num
Field
Value
Definition
0
LPBOOT
Control the reset value of OUTDIVx values in SIM_CLKDIV1 register. Larger divide value
selections produce lower average power consumption during POR, VLLSx recoveries and
reset sequencing and after reset exit. The recovery times are also extended if the
FAST_INIT option is not selected.
0
Low-power boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at
reset exit for higher divide values that produce lower power consumption at reset
exit.
• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)
are 0x7 (divide by 8)
• Flash clock divider (OUTDIV4)is 0xF (divide by 16)
1
Normal boot: OUTDIVx values in SIM_CLKDIV1 register are auto-configured at
reset exit for higher frequency values that produce faster operating frequencies at
reset exit.
• Core and system clock divider (OUTDIV1) and bus clock divider (OUTDIV2)
are 0x0 (divide by 1)
• Flash clock divider (OUTDIV4)is 0x1 (divide by 2)
6.3.4 Boot sequence
At power up, the on-chip regulator holds the system in a POR state until the input supply
is above the POR threshold. The system continues to be held in this static state until the
internally regulated supplies have reached a safe operating voltage as determined by the
LVD. The Mode Controller reset logic then controls a sequence to exit reset.
1. A system reset is held on internal logic, the RESET pin is driven out low, and the
MCG is enabled in its default clocking mode.
2. Required clocks are enabled (Core Clock, System Clock, Flash Clock, and any Bus
Clocks that do not have clock gate control reset to disabled).
3. The system reset on internal logic continues to be held, but the Flash Controller is
released from reset and begins initialization operation while the Reset Control logic
continues to drive the RESET pin out low.
4. Early in reset sequencing the NVM option byte is read and stored to the Flash
Memory module's FOPT register. If the LPBOOT is programmed for an alternate
clock divider reset value, the system/core clock is switched to a slower clock speed.
If the FAST_INIT bit is programmed clear, the Flash initialization switches to slower
clock resulting longer recovery times.
5. When Flash Initialization completes, the RESET pin is released. If RESET continues
to be asserted (an indication of a slow rise time on the RESET pin or external drive
in low), the system continues to be held in reset. Once the RESET pin is detected
high, the Core clock is enabled and the system is released from reset. EzPort mode is
selected instead of the normal CPU execution if EZP_CS is low when the internal
Chapter 6 Reset and Boot
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc.
175
