I2Sx_RCR2 field descriptions (continued)
Field
Description
24
BCD
Bit Clock Direction
Configures the direction of the bit clock.
0
Bit clock is generated externally in Slave mode.
1
Bit clock is generated internally in Master mode.
23–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–0
DIV
Bit Clock Divide
Divides down the audio master clock to generate the bit clock when configured for an internal bit clock.
The division value is (DIV + 1) * 2.
48.3.13 SAI Receive Configuration 3 Register (I2Sx_RCR3)
Address: 4002_F000h base + 8Ch offset = 4002_F08Ch
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I2Sx_RCR3 field descriptions
Field
Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
RCE
Receive Channel Enable
Enables the corresponding data channel for receive operation. A channel must be enabled before its FIFO
is accessed. Changing this field will take effect immediately for generating the FIFO request and warning
flags, but at the end of each frame for receive operation.
0
Receive data channel N is disabled.
1
Receive data channel N is enabled.
15–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
WDFL
Word Flag Configuration
Configures which word the start of word flag is set. The value written should be one less than the word
number (for example, write zero to configure for the first word in the frame). When configured to a value
greater than the Frame Size field, then the start of word flag is never set.
Memory map and register definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1272
Freescale Semiconductor, Inc.
