UARTx_S1 field descriptions (continued)
Field
Description
PF is set when PE is set and the parity of the received data does not match its parity bit. The PF is not set
in the case of an overrun condition. When PF is set, it indicates only that a dataword was received with
parity error since the last time it was cleared. There is no guarantee that the first dataword read from the
receive buffer has a parity error or that there is only one dataword in the buffer that was received with a
parity error, unless the receive buffer has a depth of one. To clear PF, read S1 and then read D.,
S2[LBKDE] is disabled,Within the receive buffer structure the received dataword is tagged if it is received
with a parity error. This information is available by reading the ED register prior to reading the D register.
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth
greater than 1, then there may be data in the receive buffer what was received with a parity error.
1
At least one dataword was received with a parity error since the last time this flag was cleared.
46.3.6 UART Status Register 2 (UARTx_S2)
The S2 register provides inputs to the MCU for generation of UART interrupts or DMA
requests. Also, this register can be polled by the MCU to check the status of these bits.
This register can be read or written at any time, with the exception of the MSBF and
RXINV bits, which should be changed by the user only between transmit and receive
packets.
Address: Base a 5h offset
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
UARTx_S2 field descriptions
Field
Description
7
LBKDIF
LIN Break Detect Interrupt Flag
LBKDIF is set when LBKDE is set and a LIN break character is detected on the receiver input. The LIN
break characters are 11 consecutive logic 0s if C1[M] = 0 or 12 consecutive logic 0s if C1[M] = 1. LBKDIF
is set after receiving the last LIN break character. LBKDIF is cleared by writing a 1 to it.
0
No LIN break character detected.
1
LIN break character detected.
6
RXEDGIF
RxD Pin Active Edge Interrupt Flag
RXEDGIF is set when an active edge occurs on the RxD pin. The active edge is falling if RXINV = 0, and
rising if RXINV=1. RXEDGIF is cleared by writing a 1 to it. See for additional details.
NOTE: The active edge is detected only in two wire mode and on receiving data coming from the RxD
pin.
0
No active edge on the receive pin has occurred.
1
An active edge on the receive pin has occurred.
Table continues on the next page...
Memory map and registers
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1146
Freescale Semiconductor, Inc.
