Freescale Semiconductor MK22FN256VDC12, Reference Manual

Page: 1141 / 1313

UARTx_C1 field descriptions (continued)
Field Description
3
WAKE
Receiver Wakeup Method Select
Determines which condition wakes the UART:
• Address mark in the most significant bit position of a received data character, or
• An idle condition on the receive pin input signal.
0 Idle line wakeup.
1 Address mark wakeup.
2
ILT
Idle Line Type Select
Determines when the receiver starts counting logic 1s as idle character bits. The count begins either after
a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s preceding
the stop bit can cause false recognition of an idle character. Beginning the count after the stop bit avoids
false idle character recognition, but requires properly synchronized transmissions.
NOTE:
• In case the UART is programmed with ILT = 1, a logic of 1'b0 is automatically shifted after a
received stop bit, therefore resetting the idle count.
• In case the UART is programmed for IDLE line wakeup (RWU = 1 and WAKE = 0), ILT has
no effect on when the receiver starts counting logic 1s as idle character bits. In idle line
wakeup, an idle character is recognized at anytime the receiver sees 10, 11, or 12 1s
depending on the M, PE, and C4[M10] fields.
0 Idle character bit count starts after start bit.
1 Idle character bit count starts after stop bit.
1
PE
Parity Enable
Enables the parity function. When parity is enabled, parity function inserts a parity bit in the bit position
immediately preceding the stop bit. This field must be set when C7816[ISO_7816E] is set/enabled.
0 Parity function disabled.
1 Parity function enabled.
0
PT
Parity Type
Determines whether the UART generates and checks for even parity or odd parity. With even parity, an
even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an odd
number of 1s clears the parity bit and an even number of 1s sets the parity bit. This field must be cleared
when C7816[ISO_7816E] is set/enabled.
0 Even parity.
1 Odd parity.
46.3.4 UART Control Register 2 (UARTx_C2)
This register can be read or written at any time.
Address: Base a 3h offset
Bit 7 6 5 4 3 2 1 0
Read
TIE TCIE RIE ILIE TE RE RWU SBK
Write
Reset 0 0 0 0 0 0 0 0
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART)
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
Freescale Semiconductor, Inc. 1141