Freescale Semiconductor MCF5329, Reference Manual, Page: 563 / 924

Liquid Crystal Display Controller (LCDC)
Freescale Semiconductor 22-43
NOTE
All parameters are defined in pixel periods , not
LCD_LSCLK periods.
Figure 22-41. Horizontal Sync Pulse Timing in TFT Mode
Figure 22-42 shows the vertical timing (timing of one frame). The delay from the end of one frame until
the beginning of the next is programmable. The memory timing signal parameters are:
• V_WAIT_1 is a delay measured in lines. For V_WAIT_1= 1 there is a delay of one LCD_HSYNC
(time = one line period) before LCD_VSYNC. The LCD_HSYNC pulse is output during the
V_WAIT_1 delay.
• For V_WIDTH (vertical sync pulse width) = 0, LCD_VSYNC encloses one LCD_HSYNC pulse.
For V_WIDTH = 2, LCD_VSYNC encloses two LCD_HSYNC pulses.
• V_WAIT_2 is a delay measured in lines. For V_WAIT_2 = 1, there is a delay of one LCD_HSYNC
(time = one line period) after LCD_VSYNC. The LCD_HSYNC pulse is output during the
V_WAIT_2 delay.
Figure 22-42. Vertical Sync Pulse Timing TFT Mode
LCD_PCR[PCD] 1 +
f
sys/3
---------------------------------------------------
⎝ ⎠
⎛ ⎞
LCD_HSYNC
LCD_OE
DATA
LCD_LSCLK
1 H3
XMAX
LCD_VSYNC
H1
V_WAIT_2
LCD_VSYNC
LCD_HSYNC
LCD_OE
V_WAIT_1
V_WIDTH
YMAX
(lines)
End of frame Beginning of frame
MCF5329 Reference Manual, Rev 3