FlexBus
MCF52277 Reference Manual, Rev. 1
Freescale Semiconductor
18-7
values differ from the other CSCRs. FB_CS0 allows address decoding for boot ROM before system
initialization.
Address: 0xFC00_8008 (CSCR0)
0xFC00_8014 (CSCR1)
0xFC00_8020 (CSCR2)
0xFC00_802C (CSCR3)
0xFC00_8038 (CSCR4)
0xFC00_8044 (CSCR5)
Access: User
read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
SWS
0
0
SWSEN
0
ASET
RDAH
WRAH
W
Reset: CSCR0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Reset: CSCR1–5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
WS
SBM
AA
PS
BEM
BSTR BSTW
0
0
0
W
Reset: CSCR0
1
1
1
1
1
1
See
Note
1
See
Note
See
Note
1
0
0
0
0
0
Reset: CSCR1–5
0
0
0
0
0
0
See
Note
1
0
0
1
0
0
0
0
0
Note:
The SBM reset value is determined by the chosen chip configuration. See SBM field description in
for more
information.
Note:
The PS reset value depends upon the chosen chip configuration. If using the default or parallel configurations
(BOOTMOD
≠
11), CSCR0[PS] resets to 11. If serial boot is chosen (BOOTMOD = 11), the CSCR0[PS] reset value is
determined by SBF_RCON[BOOTPS].
Figure 18-3. Chip-Select Control Registers (CSCR
n
)
Table 18-5. CSCR
n
Field Descriptions
Field
Description
31–26
SWS
Secondary wait states. The number of wait states inserted before an internal transfer acknowledge is generated for
a burst transfer except for the first termination, which is controlled by the wait state count. The secondary wait state
is used only if the SWSEN bit is set. Otherwise, the WS value is used for all burst transfers.
25–24
Reserved, must be cleared
23
SWSEN
Secondary wait state enable.
0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers.
1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer
secondary terminations.
22
Reserved, must be cleared
21–20
ASET
Address setup. This field controls the assertion of the chip-select with respect to assertion of a valid address and
attributes. The address and attributes are considered valid at the same time FB_TS asserts.
00 Assert FB_CS
n
on first rising clock edge after address is asserted. (Default FB_CS
n
)
01 Assert FB_CS
n
on second rising clock edge after address is asserted.
10 Assert FB_CS
n
on third rising clock edge after address is asserted.
11 Assert FB_CS
n
on fourth rising clock edge after address is asserted. (Default FB_CS0)
Summary of Contents for MCF52277
Page 22: ...MCF52277 Reference Manual Rev 1 Freescale Semiconductor xxii...
Page 32: ...MCF52277 Reference Manual Rev 0 xxxii Freescale Semiconductor...
Page 60: ...Signal Descriptions MCF52277 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 128: ...Static RAM SRAM MCF52277 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 140: ...Clock Module MCF52277 Reference Manual Rev 1 7 12 Freescale Semiconductor...
Page 172: ...Chip Configuration Module CCM MCF52277 Reference Manual Rev 1 9 16 Freescale Semiconductor...
Page 180: ...Serial Boot Facility SBF MCF52277 Reference Manual Rev 1 10 8 Freescale Semiconductor...
Page 188: ...Reset Controller Module MCF52277 Reference Manual Rev 1 11 8 Freescale Semiconductor...
Page 210: ...Crossbar Switch XBS MCF52277 Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 542: ...FlexCAN MCF52277 Reference Manual Rev 1 23 32 Freescale Semiconductor...
Page 724: ...UART Modules MCF52277 Reference Manual Rev 1 30 34 Freescale Semiconductor...
Page 740: ...I2 C Interface MCF52277 Reference Manual Rev 1 31 16 Freescale Semiconductor...
Page 790: ...Debug Module MCF52277 Reference Manual Rev 1 32 50 Freescale Semiconductor...
