Freescale Semiconductor MCF52100, Reference Manual

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Pulse-Width Modulation (PWM) Module
MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
26-18 Freescale Semiconductor
Preliminary
26.3.2.5 Left-Aligned Outputs
The PWM timer provides the choice of two types of outputs: left- or center-aligned. They are selected with
the PWMCAE[CAE
n ] bits. If the CAE n bit is cleared, the corresponding PWM output is left-aligned.
In left-aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two
registers, a duty register and a period register, as shown in the block diagram in
Figure 26-15 . When the
PWM counter matches the duty register, the output flip-flop changes state causing the PWM waveform to
also change state. A match between the PWM counter and the period register resets the counter and the
output flip-flop, as shown in
Figure 26-16 , as well as performing a load from the double buffer period and
duty register to the associated registers, as described in Figure 26.3.2.3 . The counter counts from 0 to the
value in the period register minus 1.
NOTE
Changing the PWM output mode from left-aligned to center-aligned output
(or vice versa) while channels are operating can cause irregularities in the
PWM output. It is recommended to program the output mode before
enabling the PWM channel.
Figure 26-16. PWM Left-Aligned Output Waveform
To calculate the output frequency in left-aligned output mode for a particular channel, take the selected
clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register
for that channel.
Eqn. 26-7
The PWM n duty cycle (high time as a percentage of period) is expressed as:
Eqn. 26-8
26.3.2.5.1 Left-Aligned Output Example
As an example of a left-aligned output, consider the following case:
Clock source = internal bus clock, where internal bus clock = 40 MHz (25 ns period)
PPOL n = 0, PWMPER n = 4, PWMDTY n = 1
PWM n frequency = 40 MHz
÷
4 = 10 MHz
PWM n period = 100 ns
The output waveform generated is below:
PWMDTY n
Period = PWMPER n
PPOL n = 0
PPOL n = 1
PWM n frequency
Clock (A, B, SA, or SB)
PWMPER n
----------------------------------------------------------
=
Duty Cycle 1 PWMPOL PPOL n
[ ]
PWMDTY n
PWMPER n
-------------------------------
– –
⎝ ⎠
⎛ ⎞
100%
×
=
PWMn Duty Cycle 1
1
4
---
–
⎝ ⎠
⎛ ⎞
100% 75% =
×
=